PIC18F4580-I/ML Microchip Technology, PIC18F4580-I/ML Datasheet - Page 156
PIC18F4580-I/ML
Manufacturer Part Number
PIC18F4580-I/ML
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,44PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F2221-ISO.pdf
(46 pages)
3.PIC18F4480-IPT.pdf
(490 pages)
4.PIC18F4480-IPT.pdf
(8 pages)
5.PIC18F4480-IPT.pdf
(6 pages)
6.PIC18F4480-IPT.pdf
(6 pages)
Specifications of PIC18F4580-I/ML
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT44QFN2 - SOCKET TRAN ICE 44QFN/40DIPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN444-1001 - DEMO BOARD FOR PICMICRO MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC18F2221-ISO PDF datasheet #2
- PIC18F4480-IPT PDF datasheet #3
- PIC18F4480-IPT PDF datasheet #4
- PIC18F4480-IPT PDF datasheet #5
- PIC18F4480-IPT PDF datasheet #6
- Current page: 156 of 490
- Download datasheet (9Mb)
PIC18F2480/2580/4480/4580
13.1
Timer1 can operate in one of these modes:
• Timer
• Synchronous Counter
• Asynchronous Counter
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>). When TMR1CS is cleared
(= 0), Timer1 increments on every internal instruction
FIGURE 13-1:
FIGURE 13-2:
DS39637D-page 156
T1OSO/T13CKI
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
T1OSO/T13CKI
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
Timer1 Operation
T1OSI
T1OSI
Timer1 Oscillator
T1OSCEN
T1CKPS<1:0>
T1SYNC
TMR1ON
TIMER1 BLOCK DIAGRAM
TIMER1 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)
Timer1 Oscillator
T1OSCEN
T1CKPS<1:0>
T1SYNC
TMR1ON
(1)
(1)
TMR1CS
(CCP Special Event Trigger)
TMR1CS
Clear TMR1
(CCP Special Event Trigger)
Clear TMR1
Clock
Internal
F
Clock
Internal
OSC
F
OSC
/4
/4
On/Off
1
0
1
0
Prescaler
1, 2, 4, 8
Prescaler
cycle (F
on every rising edge of the Timer1 external clock input
or the Timer1 oscillator, if enabled.
When Timer1 is enabled, the RC1/T1OSI and RC0/
T1OSO/T13CKI pins become inputs. This means the
values of TRISC<1:0> are ignored and the pins are
read as ‘0’.
1, 2, 4, 8
2
2
OSC
TMR1L
TMR1L
/4). When the bit is set, Timer1 increments
8
Sleep Input
Synchronize
Sleep Input
8
Synchronize
Detect
Detect
High Byte
High Byte
TMR1H
TMR1
TMR1
8
© 2009 Microchip Technology Inc.
8
8
1
0
Internal Data Bus
1
1
0
Read TMR1L
Write TMR1L
on Overflow
on Overflow
TMR1IF
TMR1IF
Set
Set
Timer1
On/Off
Timer1
On/Off
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