PIC18F8722T-I/PT Microchip Technology, PIC18F8722T-I/PT Datasheet - Page 12
PIC18F8722T-I/PT
Manufacturer Part Number
PIC18F8722T-I/PT
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,80PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.DV164136.pdf
(6 pages)
3.DV164136.pdf
(446 pages)
4.PIC18F8627T-IPT.pdf
(44 pages)
5.PIC18LF6627-IPT.pdf
(16 pages)
Specifications of PIC18F8722T-I/PT
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164136 - DEVELOPMENT KIT FOR PIC18XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F8722T-I/PT
Manufacturer:
MICROCHIP
Quantity:
12 000
Company:
Part Number:
PIC18F8722T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
PIC18F6627/6722/8627/8722
37. Module: Reset
DS80221C-page 12
This version of silicon does not support the func-
tionality described in Note 1 of parameter D002 in
Section 28.1 “DC Characteristics: Supply
Voltage” of the data sheet. The RAM content may
be altered during a Reset event if the following
conditions are met.
• Device is accessing RAM.
• Asynchronous Reset (i.e., WDT, BOR or MCLR
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
occurs when a write operation is being
executed (start of a Q4 cycle).
38. Module: External Memory Bus
The A<19:16> EMB address lines and Read/Write
control pins (OE, WRH and WRL) are released to
their respective inactive states at the same time,
violating the timing condition mentioned in
Figure 28-8 and Figure 28-9 in the Device Data
Sheet. This may result in a peripheral device on
the bus detecting an address change when a write/
read is initiated. The bus capacitance and signal
delay on the address and control lines can affect
the probability of invalid detection.
Work around
Two work arounds are available:
1. Use a latch based on the falling edge of ALE to
2. Add a delay circuit to extend the valid time for
hold the A<19:16> signals.
A<19:16> signals to ensure the address is
valid until read/write signals go inactive.
© 2006 Microchip Technology Inc.