XC4010E-3PQ160I Xilinx Inc, XC4010E-3PQ160I Datasheet - Page 31

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XC4010E-3PQ160I

Manufacturer Part Number
XC4010E-3PQ160I
Description
IC FPGA I-TEMP 5V 3SPD 160-PQFP - XC4010E-3PQ160I
Manufacturer
Xilinx Inc
Series
XC4000E/Xr
Datasheet

Specifications of XC4010E-3PQ160I

Number Of Logic Elements/cells
950
Number Of Labs/clbs
400
Total Ram Bits
12800
Number Of I /o
129
Number Of Gates
10000
Voltage - Supply
4.5 V ~ 5.5 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
160-BQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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IOB inputs and outputs interface with the octal lines via the
single-length interconnect lines. Single-length lines are
also used for communication between the octals and dou-
ble-length lines, quads, and longlines within the CLB array.
Segmentation into buffered octals was found to be optimal
for distributing signals over long distances around the
device.
Global Nets and Buffers
Both the XC4000E and the XC4000X have dedicated glo-
bal networks. These networks are designed to distribute
clocks and other high fanout control signals throughout the
devices with minimal skew. The global buffers are
described in detail in the following sections. The text
descriptions and diagrams are summarized in
The table shows which CLB and IOB clock pins can be
sourced by which global buffers.
In both XC4000E and XC4000X devices, placement of a
library symbol called BUFG results in the software choos-
ing the appropriate clock buffer, based on the timing
requirements of the design. The detailed information in
these sections is included only for reference.
Global Nets and Buffers (XC4000E only)
Four vertical longlines in each CLB column are driven
exclusively by special global buffers.
in addition to the vertical longlines used for standard inter-
connect. The four global lines can be driven by either of two
types of global buffers. The clock pins of every CLB and
IOB can also be sourced from local interconnect.
Table 15: Clock Pin Access
L = Left, R = Right, T = Top, B = Bottom
May 14, 1999 (Version 1.6)
All CLBs in Quadrant
All CLBs in Device
IOBs on Adjacent Vertical
Half Edge
IOBs on Adjacent Vertical
Full Edge
IOBs on Adjacent Horizontal
Half Edge (Direct)
IOBs on Adjacent Horizontal
Half Edge (through CLB globals)
IOBs on Adjacent Horizontal
Full Edge (through CLB globals)
R
Product Obsolete or Under Obsolescence
XC4000E and XC4000X Series Field Programmable Gate Arrays
These longlines are
BUFGP
Table
XC4000E
15.
BUFGS
Two different types of clock buffers are available in the
XC4000E:
• Primary Global Buffers (BUFGP)
• Secondary Global Buffers (BUFGS)
Four Primary Global buffers offer the shortest delay and
negligible skew. Four Secondary Global buffers have
slightly longer delay and slightly more skew due to poten-
tially heavier loading, but offer greater flexibility when used
to drive non-clock CLB inputs.
The Primary Global buffers must be driven by the
semi-dedicated pads. The Secondary Global buffers can
be sourced by either semi-dedicated pads or internal nets.
Each CLB column has four dedicated vertical Global lines.
Each of these lines can be accessed by one particular Pri-
mary Global buffer, or by any of the Secondary Global buff-
ers, as shown in
one Primary buffer and one Secondary buffer.
IOBs along the left and right edges have four vertical global
longlines. Top and bottom IOBs can be clocked from the
global lines in the adjacent CLB column.
A global buffer should be specified for all timing-sensitive
global signal distribution. To use a global buffer, place a
BUFGP (primary buffer), BUFGS (secondary buffer), or
BUFG (either primary or secondary buffer) element in a
schematic or in HDL code.
attribute or property to direct placement to the designated
location. For example, attach a LOC=L attribute or property
to a BUFGS symbol to direct that a buffer be placed in one
of the two Secondary Global buffers on the left edge of the
device, or a LOC=BL to indicate the Secondary Global
buffer on the bottom edge of the device, on the left.
BUFGLS
Figure
XC4000X
BUFGE
L & R
34. Each corner of the device has
If desired, attach a LOC
BUFGE
T & B
connect
Local
Inter-
6-35
6

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