EVAL-ADXL346Z Analog Devices Inc, EVAL-ADXL346Z Datasheet - Page 26

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EVAL-ADXL346Z

Manufacturer Part Number
EVAL-ADXL346Z
Description
Inertial Sensor Evaluation System
Manufacturer
Analog Devices Inc
Datasheets

Specifications of EVAL-ADXL346Z

Silicon Manufacturer
Analog Devices
Silicon Core Number
ADXL346
Kit Application Type
Sensing - Motion / Vibration / Shock
Application Sub Type
Accelerometer
Silicon Family Name
IMEMS
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
ADXL346
Register 0x31—DATA_FORMAT (Read/Write)
D7
SELF_TEST
The DATA_FORMAT register controls the presentation of data
to Register 0x32 through Register 0x37. All data, except that for
the ±16 g range, must be clipped to avoid rollover.
SELF_TEST Bit
A setting of 1 in the SELF_TEST bit applies a self-test force to
the sensor, causing a shift in the output data. A value of 0 disables
the self-test force.
SPI Bit
A value of 1 in the SPI bit sets the device to 3-wire SPI mode,
and a value of 0 sets the device to 4-wire SPI mode.
INT_INVERT Bit
A value of 0 in the INT_INVERT bit sets the interrupts to active
high, and a value of 1 sets the interrupts to active low.
FULL_RES Bit
When this bit is set to a value of 1, the device is in full resolution
mode, where the output resolution increases with the g range
set by the range bits to maintain a 4 mg/LSB scale factor. When
the FULL_RES bit is set to 0, the device is in 10-bit mode, and
the range bits determine the maximum g range and scale factor.
Justify Bit
A setting of 1 in the justify bit selects left-justified (MSB) mode,
and a setting of 0 selects right-justified mode with sign extension.
Range Bits
These bits set the g range as described in Table 21.
Table 21. g Range Setting
D1
0
0
1
1
Register 0x32 to Register 0x37—DATAX0, DATAX1,
DATAY0, DATAY1, DATAZ0, DATAZ1 (Read Only)
These six bytes (Register 0x32 to Register 0x37) are eight bits
each and hold the output data for each axis. Register 0x32 and
Register 0x33 hold the output data for the x-axis, Register 0x34 and
Register 0x35 hold the output data for the y-axis, and Register 0x36
and Register 0x37 hold the output data for the z-axis. The output
data is twos complement, with DATAx0 as the least significant byte
Setting
D0
0
1
0
1
D6
SPI
D5
INT_INVERT
g Range
±2 g
±4 g
±8 g
±16 g
D4
0
D3
FULL_RES
D2
Justify
D1
Range
Rev. A | Page 26 of 40
D0
and DATAx1 as the most significant byte, where x represents X,
Y, or Z. The DATA_FORMAT register (Address 0x31) controls
the format of the data. It is recommended that a multiple-byte
read of all registers be performed to prevent a change in data
between reads of sequential registers.
Register 0x38—FIFO_CTL (Read/Write)
D7
FIFO_MODE
FIFO_MODE Bits
These bits set the FIFO mode, as described in Table 22.
Table 22. FIFO Modes
D7
0
0
1
1
Trigger Bit
A value of 0 in the trigger bit links the trigger event of trigger mode
to INT1, and a value of 1 links the trigger event to INT2.
Samples Bits
The function of these bits depends on the FIFO mode selected (see
Table 23). Entering a value of 0 in the samples bits immediately
sets the watermark bit in the INT_SOURCE register (Address
0x30), regardless of which FIFO mode is selected. Undesirable
operation may occur if a value of 0 is used for the samples bits
when trigger mode is used.
Table 23. Samples Bits Functions
FIFO Mode
Bypass
FIFO
Stream
Trigger
Setting
D6
0
1
0
1
D6
D5
Trigger
Mode
Bypass
FIFO
Stream
Trigger
Samples Bits Function
None.
Specifies how many FIFO entries are needed to
trigger a watermark interrupt.
Specifies how many FIFO entries are needed to
trigger a watermark interrupt.
Specifies how many FIFO samples are retained in
the FIFO buffer before a trigger event.
D4
Function
FIFO is bypassed.
FIFO collects up to 32 values and then
stops collecting data, collecting new
data only when FIFO is not full.
FIFO holds the last 32 data values.
When FIFO is full, the oldest data is
overwritten with newer data.
When triggered by the trigger bit,
FIFO holds the last data samples
before the trigger event and then
continues to collect data until FIFO is
full. New data is collected only when
FIFO is not full.
D3
Samples
D2
D1
D0

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