AGLN-Z-NANO-KIT Actel, AGLN-Z-NANO-KIT Datasheet - Page 17

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AGLN-Z-NANO-KIT

Manufacturer Part Number
AGLN-Z-NANO-KIT
Description
MCU, MPU & DSP Development Tools IGLOO nano Starter Kit
Manufacturer
Actel
Datasheet

Specifications of AGLN-Z-NANO-KIT

Processor To Be Evaluated
AGLN250
Processor Series
IGLOO nano
Interface Type
USB
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
- 20 C
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
2 – Power
Power Modes
The IGLOO nano development board is powered through an external voltage power brick or USB. If both
the power brick and USB are plugged in, the development board will power through the power brick. If
the power brick is unplugged, the board will seamlessly switch to power through the USB. In the USB
option, in-rush current meets USB specifications. The power brick option is provided in cases when
100% of total I/Os are utilized.
The development board has an input of a 5 V supply from the power brick. Protection diodes are used to
protect against negative voltage. Three voltage rails (3.3 V, 2.5 V, and 1.5 V) are provided.
The regulator can be switched between the 1.5 V and 1.2 V rail because the FPGA core functions at
1.2 V, but is programmed at 1.5 V. A green LED will glow whenever the USB power is connected.
Table 2-1
Table 2-1 • Power Regulator Current Ratings
Figure 2-1
Figure 2-1 • Power LED Schematic
In addition to the board, the IGLOO nano FPGA offers power advantages. Some key power advantages
of the IGLOO nano FPGAs are as follows:
Regulator
3.3 V
2.5 V
1.5 V
Flash*Freeze technology enables easy entry and exit from the static low power mode, whereas
IGLOO consumes as little as 5 µW while retaining the contents of the system memory and data
registers.
Sleep and shutdown modes enable the IGLOO nano FPGA core power supply (or all power
supplies) to be powered down when functionality is not required, while the rest of the system
remains powered.
The user low static ICC macro (ULSICC) reduces IGLOO nano FPGA dynamic and static power
consumption. The ULSICC macro, when enabled, disables the FlashROM, reducing the overall
power of the device.
gives the current ratings for each voltage rail.
shows the schematic for the power LED9.
R e v i s i o n 2
VCC_vbus
R38
R38
560R-0603
560R-0603
LED9
LED9
GREEN SMD LED - 1206
GREEN SMD LED - 1206
USB Connected
Current Rating
2A
1A
1A
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