EVAL-ADAU1761Z Analog Devices Inc, EVAL-ADAU1761Z Datasheet
EVAL-ADAU1761Z
Specifications of EVAL-ADAU1761Z
Available stocks
Related parts for EVAL-ADAU1761Z
EVAL-ADAU1761Z Summary of contents
Page 1
FEATURES SigmaDSP 28-/56-bit, 50 MIPS digital audio processor Fully programmable with SigmaStudio graphical tool 24-bit stereo audio ADC and DAC: >98 dB SNR Sampling rates from 8 kHz to 96 kHz Low power record playback, 48 ...
Page 2
ADAU1761 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 Specifications..................................................................................... 4 Analog Performance Specifications ........................................... 4 Power Supply Specifications........................................................ 7 Typical Current Consumption.................................................... 8 Typical Power Management ...
Page 3
REVISION HISTORY 9/10—Rev Rev. C Changes to Figure 1...........................................................................1 5/10—Rev Rev. B Changes to Burst Mode Writing and Reading Section ..............38 Changes to Table 33 ........................................................................51 Added R67: Dejitter Control, 16,438 (0x4036) Section .............79 12/09—Rev. 0 ...
Page 4
ADAU1761 SPECIFICATIONS Supply voltage (AVDD 25°C, master clock = 12.288 MHz (48 kHz f A bandwidth = kHz, word width = 24 bits, C unless otherwise noted. Performance of all channels ...
Page 5
Parameter PSEUDO-DIFFERENTIAL PGA INPUT Full-Scale Input Voltage (0 dB) Dynamic Range With A-Weighted Filter (RMS) No Filter (RMS) Total Harmonic Distortion + Noise Signal-to-Noise Ratio With A-Weighted Filter (RMS) No Filter (RMS) Volume Control Step Volume Control Range PGA Boost ...
Page 6
ADAU1761 Parameter Interchannel Isolation Common-Mode Rejection Ratio MICROPHONE BIAS Bias Voltage 0.65 × AVDD 0.90 × AVDD Bias Current Source Noise in the Signal Bandwidth DIGITAL-TO-ANALOG CONVERTERS DAC Resolution Digital Attenuation Step Digital Attenuation Range DAC TO LINE OUTPUT Full-Scale ...
Page 7
Parameter DAC TO HEADPHONE/EARPIECE OUTPUT Full-Scale Output Voltage (0 dB) Total Harmonic Distortion + Noise 16 Ω load 32 Ω load Power Supply Rejection Ratio Interchannel Isolation REFERENCE Common-Mode Reference Output POWER SUPPLY SPECIFICATIONS Table 2. Parameter SUPPLIES Voltage Digital ...
Page 8
ADAU1761 TYPICAL CURRENT CONSUMPTION Master clock = 12.288 MHz, input sample rate = 48 kHz, input tone = 1 kHz, normal power management settings, ADC input @ −1 dBFS, DAC input @ 0 dBFS. For total power consumption, add the ...
Page 9
TYPICAL POWER MANAGEMENT MEASUREMENTS Master clock = 12.288 MHz, integer PLL, input sample rate = 48 kHz, input tone = 1 kHz. Pseudo-differential input to ADCs, DACs to line output with 10 kΩ load. ADC input @ −1 dBFS, DAC ...
Page 10
ADAU1761 DIGITAL FILTERS Table 5. Parameter ADC DECIMATION FILTER Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Attenuation Group Delay DAC INTERPOLATION FILTER Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Attenuation Group Delay DIGITAL INPUT/OUTPUT SPECIFICATIONS −40°C ...
Page 11
DIGITAL TIMING SPECIFICATIONS −40°C < T < +85°C, IOVDD = 3.3 V ± 10%. A Table 7. Digital Timing Parameter t MIN MASTER CLOCK 24 18.5 MP SERIAL PORT t 5 ...
Page 12
ADAU1761 DIGITAL TIMING DIAGRAMS t BIH BCLK t BIL t LIS LRCLK t SIS DAC_SDATA LEFT-JUSTIFIED MSB MODE t SIH DAC_SDATA MODE DAC_SDATA RIGHT-JUSTIFIED MODE 8-BIT CLOCKS (24-BIT DATA) 12-BIT CLOCKS (20-BIT DATA) 14-BIT CLOCKS (18-BIT DATA) ...
Page 13
CLS t CLATCH CCPH CCLK CDATA t CDS COUT t SCH SDA t SCL CLK DATA1/ DATA2 DATA1 t CCPL t CDH Figure 4. SPI Port Timing SCR SCLH SCS SCLL SCF 2 ...
Page 14
ADAU1761 ABSOLUTE MAXIMUM RATINGS Table 8. Parameter Power Supply (AVDD) Input Current (Except Supply Pins) Analog Input Voltage (Signal Pins) Digital Input Voltage (Signal Pins) Operating Temperature Range Storage Temperature Range Stresses above those listed under Absolute Maximum Ratings may ...
Page 15
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 10. Pin Function Descriptions 1 Pin No. Mnemonic Type 1 IOVDD PWR 2 MCLK D_IN 3 ADDR0/CLATCH D_IN 4 JACKDET/MICIN D_IN 5 MICBIAS A_OUT 6 LAUX A_IN 7 CM A_OUT 8 AVDD PWR 9 ...
Page 16
ADAU1761 1 Pin No. Mnemonic Type 19 RHP A_OUT 20 LHP A_OUT 21 MONOOUT A_OUT 22 AGND PWR 23 AVDD PWR 24 DVDDOUT PWR 25 DGND PWR 26 ADC_SDATA/GPIO1 D_IO 27 DAC_SDATA/GPIO0 D_IO 28 BCLK/GPIO2 D_IO 29 LRCLK/GPIO3 D_IO 30 ...
Page 17
TYPICAL PERFORMANCE CHARACTERISTICS –60 –50 –40 –30 DIGITAL 1kHz INPUT SIGNAL (dBFS) Figure 8. Headphone Amplifier Power vs. Input Level, 16 Ω Load 18 16 ...
Page 18
ADAU1761 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 0 0.1 0.2 0.3 0.4 0.5 0.6 FREQUENCY (NORMALIZED TO Figure 14. ADC Decimation Filter, 128× Oversampling, Normalized –10 –20 –30 –40 –50 –60 –70 ...
Page 19
FREQUENCY (NORMALIZED TO Figure 20. DAC Interpolation Filter, 128× Oversampling, Normalized −10 −20 −30 −40 −50 −60 −70 −80 ...
Page 20
ADAU1761 SYSTEM BLOCK DIAGRAMS THE INPUT CAPACITOR VALUE DEPENDS ON THE INPUT IMPEDANCE, WHICH VARIES WITH THE VOLUME SETTING. 10µF LEFT MICROPHONE 10µF 2kΩ 2kΩ 10µF RIGHT MICROPHONE 10µF JACK DETECTION SIGNAL AUX LEFT 1kΩ AUX RIGHT 1kΩ CLOCK SOURCE ...
Page 21
THE INPUT CAPACITOR VALUE DEPENDS ON THE INPUT IMPEDANCE, WHICH VARIES WITH THE VOLUME SETTING SINGLE-ENDED 10µF ANALOG OUTPUT MICROPHONE CM GND V DD SINGLE-ENDED 10µF ANALOG OUTPUT MICROPHONE CM GND JACK DETECTION SIGNAL AUX LEFT 10µF 1kΩ ...
Page 22
ADAU1761 BCLK CLK CM V DIGITAL DATA DD MICROPHONE 0.1µF L/R SELECT GND BCLK CLK V DATA DIGITAL DD MICROPHONE 0.1µF L/R SELECT GND AUX LEFT 10µF 1kΩ 10µF AUX RIGHT 1kΩ 49.9Ω CLOCK SOURCE Figure 28. System Block Diagram ...
Page 23
THEORY OF OPERATION The ADAU1761 is a low power audio codec with an integrated stream-oriented DSP core, making it an all-in-one package that offers high quality audio, low power, small size, and many advanced features. The stereo ADC and stereo ...
Page 24
ADAU1761 STARTUP, INITIALIZATION, AND POWER This section describes the procedure for properly starting up the ADAU1761. The following sequence provides a high level approach to the proper initiation of the system. 1. Apply power to the ADAU1761. 2. Lock the ...
Page 25
Case 2: PLL Is Used The core clock to the entire chip is off during the PLL lock acquisition period. The user can poll the lock bit to determine when the PLL has locked. After lock is acquired, the ADAU1761 ...
Page 26
ADAU1761 CLOCKING AND SAMPLING RATES R1: PLL CONTROL REGISTER ÷ X MCLK × N/M) CORE CLOCK Clocks for the converters, the serial ports, and the DSP are derived from the core clock. The core clock can be derived ...
Page 27
SAMPLING RATES The ADCs, DACs, and serial port share a common sampling rate that is set in Register R17 (Converter Control 0 register, Address 0x4017). The CONVSR[2:0] bits set the sampling rate as a ratio of the base sampling frequency. ...
Page 28
ADAU1761 Bits Bit Name Description [10:9] X[1:0] PLL input clock divider 00 (default Type PLL operation mode 0: Integer (default) 1: Fractional 1 Lock ...
Page 29
RECORD SIGNAL PATH JACKDET/MICIN PGA LINN –12dB TO LINP +35.25dB ALCSEL[2:0] LDVOL[5:0] ALC CONTROL LAUX RAUX PGA RINP –12dB TO RINN +35.25dB ALCSEL[2:0] RDVOL[5:0] ALC CONTROL INPUT SIGNAL PATHS The ADAU1761 can accept both line level and microphone inputs. The ...
Page 30
ADAU1761 Analog Microphone Inputs For microphone inputs, configure the part in either stereo pseudo-differential mode or stereo full differential mode. The LINN and LINP pins are the inverting and noninverting inputs for the left channel, respectively. The RINN and RINP ...
Page 31
Digital Microphone Input When using a digital microphone connected to the JACKDET/ MICIN pin, the JDFUNC[1:0] bits in Register R2 (Address 0x4008) must be set enable the microphone input and disable the jack detection function. The ADAU1761 ...
Page 32
ADAU1761 AUTOMATIC LEVEL CONTROL (ALC) The ADAU1761 contains a hardware automatic level control (ALC). The ALC is designed to continuously adjust the PGA gain to keep the recording volume constant as the input level varies. For optimal noise performance, the ...
Page 33
INPUT GAIN OUTPUT HOLD DECAY TIME TIME Figure 38. Basic ALC Operation MAX GAIN = 30dB MAX GAIN = 24dB MAX GAIN = 18dB TARGET INPUT LEVEL (dB) Figure 39. Effect of Varying the Maximum Gain Parameter NOISE GATE FUNCTION ...
Page 34
ADAU1761 Noise Gate Mode 2 (see Figure 42) is selected by setting the NGTYP[1:0] bits to 10. In this mode, the ADAU1761 improves the sound of the noise gate operation by first fading the PGA gain over a period of ...
Page 35
PLAYBACK SIGNAL PATH MX3G1[3:0] LEFT INPUT MIXER –15dB TO +6dB MX3G2[3:0] RIGHT INPUT MIXER –15dB TO +6dB MX3AUXG[3:0] LAUX –15dB TO +6dB LEFT DAC RIGHT DAC MX4G1[3:0] LEFT INPUT MIXER –15dB TO +6dB MX4G2[3:0] RIGHT INPUT MIXER –15dB TO +6dB ...
Page 36
ADAU1761 HEADPHONE OUTPUT The LHP and RHP pins can be driven by either a line output driver or a headphone driver by setting the HPMODE bit in Register R30 (playback headphone right volume control register, Address 0x4024). The headphone outputs ...
Page 37
Jack Detection When the JACKDET/MICIN pin is set to the jack detect func- tion, a flag on this pin can be used to mute the line outputs when headphones are plugged into the jack. This pin can be configured in ...
Page 38
ADAU1761 CONTROL PORTS The ADAU1761 can operate in one of two control modes: • control • SPI control The ADAU1761 has both a 4-wire SPI control port and a 2 2-wire I C bus control port. Both ...
Page 39
The R/ W bit determines the direction of the data. A Logic 0 on the LSB of the first byte means that the master will write infor- mation to the peripheral, whereas a Logic 1 means that the master will ...
Page 40
ADAU1761 Read and Write Operations Figure 51 shows the format of a single-word write operation. Every ninth clock pulse, the ADAU1761 issues an acknowledge by pulling SDA low. Figure 52 shows the format of a burst mode ...
Page 41
SPI PORT 2 By default, the ADAU1761 mode, but it can be put into SPI control mode by pulling CLATCH low three times. This is done by performing three dummy writes to the SPI port (the ...
Page 42
ADAU1761 SERIAL DATA INPUT/OUTPUT PORTS The flexible serial data input and output ports of the ADAU1761 can be set to accept or transmit data in 2-channel format 4-channel or 8-channel TDM stream to interface to external ADCs ...
Page 43
LEFT CHANNEL LRCLK BCLK SDATA MSB LEFT CHANNEL LRCLK BCLK MSB SDATA Figure 59. Left-Justified Mode—16 Bits to 24 Bits per Channel LEFT CHANNEL LRCLK BCLK SDATA MSB Figure 60. Right-Justified Mode—16 Bits to 24 Bits per Channel LRCLK BCLK ...
Page 44
ADAU1761 APPLICATIONS INFORMATION POWER SUPPLY BYPASS CAPACITORS Each analog and digital power supply pin should be bypassed to its nearest appropriate ground pin with a single 100 nF capaci- tor. The connections to each side of the capacitor should be ...
Page 45
DSP CORE SIGNAL PROCESSING The ADAU1761 is designed to provide all audio signal processing functions commonly used in stereo or mono low power record and playback systems. The signal processing flow is designed using the SigmaStudio software, which allows graphical ...
Page 46
ADAU1761 NUMERIC FORMATS DSP systems commonly use a standard numeric format. Fractional numeric systems are specified by an A.B format, where A is the number of bits to the left of the decimal point and B is the number of ...
Page 47
PROGRAM RAM, PARAMETER RAM, AND DATA RAM Table 26. RAM Map and Read/Write Modes Memory Size Parameter RAM 1024 × 32 Program RAM 1024 × 40 Table 26 shows the RAM map (the ADAU1761 register map is provided in the ...
Page 48
ADAU1761 Table 27. Parameter RAM Read/Write Format (Single Address) Byte 0 Byte 1 chip_adr[6:0], R/W param_adr[15:8] Table 28. Parameter RAM Block Read/Write Format (Burst Mode) Byte 0 Byte 1 chip_adr[6:0], R/W param_adr[15:8] Table 29. Program RAM Read/Write Format (Single Address) ...
Page 49
SOFTWARE SLEW When the values of signal processing parameters are changed abruptly in real time, they sometimes cause pop and click sounds to appear on the audio outputs. To avoid pops and clicks, some algorithms in SigmaStudio implement a software ...
Page 50
ADAU1761 GENERAL-PURPOSE INPUT/OUTPUT The serial data input/output pins (Pin 26 to Pin 29) are shared with the general-purpose input/output function. Each of these four pins can be set to only one of these functions. The function of these pins is ...
Page 51
CONTROL REGISTERS Table 33. Register Map Reg Address Name Bit 7 R0 0x4000 Clock control R1 0x4002 PLL control Reserved R2 0x4008 Dig mic/jack detect R3 0x4009 Rec power mgmt Reserved R4 0x400A Rec Mixer Left 0 Reserved R5 0x400B ...
Page 52
ADAU1761 Reg Address Name Bit 7 R47 0x40C4 CRC enable R48 0x40C6 GPIO0 pin control R49 0x40C7 GPIO1 pin control R50 0x40C8 GPIO2 pin control R51 0x40C9 GPIO3 pin control R52 0x40D0 Watchdog enable R53 0x40D1 Watchdog value R54 0x40D2 ...
Page 53
R1: PLL Control, 16,386 (0x4002) Byte Bit 7 Bit Reserved 5 Table 35. PLL Control Register Byte Bits Bit Name Description 0 [7:0] M[15:8] PLL denominator MSB. This value is concatenated with M[7:0] to ...
Page 54
ADAU1761 R2: Digital Microphone/Jack Detection Control, 16,392 (0x4008) Bit 7 Bit 6 Bit 5 JDDB[1:0] Table 36. Digital Microphone/Jack Detection Control Register Bits Bit Name Description [7:6] JDDB[1:0] Jack detect debounce time. Setting [5:4] JDFUNC[1:0] JACKDET/MICIN ...
Page 55
R4: Record Mixer Left (Mixer 1) Control 0, 16,394 (0x400A) This register controls the gain of single-ended inputs for the left channel record path. The left channel record mixer is referred to as Mixer 1. Bit 7 Bit 6 Bit ...
Page 56
ADAU1761 R5: Record Mixer Left (Mixer 1) Control 1, 16,395 (0x400B) This register controls the gain boost of the left channel differential PGA input and the gain for the left channel auxiliary input in the record path. The left channel ...
Page 57
R6: Record Mixer Right (Mixer 2) Control 0, 16,396 (0x400C) This register controls the gain of single-ended inputs for the right channel record path. The right channel record mixer is referred to as Mixer 2. Bit 7 Bit 6 Bit ...
Page 58
ADAU1761 R7: Record Mixer Right (Mixer 2) Control 1, 16,397 (0x400D) This register controls the gain boost of the right channel differential PGA input and the gain for the right channel auxiliary input in the record path. The right channel ...
Page 59
R9: Right Differential Input Volume Control, 16,399 (0x400F) This register enables the differential path and sets the volume control for the right differential PGA input. Bit 7 Bit 6 Bit 5 Table 43. Right Differential Input Volume Control Register Bits ...
Page 60
ADAU1761 R11: ALC Control 0, 16,401 (0x4011) Bit 7 Bit 6 Bit 5 PGASLEW[1:0] Table 45. ALC Control 0 Register Bits Bit Name Description [7:6] PGASLEW[1:0] PGA volume slew time when the ALC is off. The slew time is the ...
Page 61
R12: ALC Control 1, 16,402 (0x4012) Bit 7 Bit 6 Bit 5 ALCHOLD[3:0] Table 46. ALC Control 1 Register Bits Bit Name Description [7:4] ALCHOLD[3:0] ALC hold time. The ALC hold time is the amount of time that the ALC ...
Page 62
ADAU1761 R13: ALC Control 2, 16,403 (0x4013) Bit 7 Bit 6 Bit 5 ALCATCK[3:0] Table 47. ALC Control 2 Register Bits Bit Name Description [7:4] ALCATCK[3:0] ALC attack time. The attack time sets how fast the ALC starts attenuating after ...
Page 63
R14: ALC Control 3, 16,404 (0x4014) Bit 7 Bit 6 Bit 5 NGEN NGTYP[1:0] Table 48. ALC Control 3 Register Bits Bit Name Description [7:6] NGTYP[1:0] Noise gate type. When the input signal falls below the threshold for 250 ms, ...
Page 64
ADAU1761 R16: Serial Port Control 1, 16,406 (0x4016) Bit 7 Bit 6 Bit 5 BPF[2:0] Table 50. Serial Port Control 1 Register Bits Bit Name Description [7:5] BPF[2:0] Number of bit clock cycles per LRCLK audio frame. Setting 000 001 ...
Page 65
R17: Converter Control 0, 16,407 (0x4017) Bit 7 Bit 6 Bit 5 Reserved DAPAIR[1:0] Table 51. Converter Control 0 Register Bits Bit Name Description [6:5] DAPAIR[1:0] On-chip DAC serial data selection in TDM 4 or TDM 8 mode. Setting 00 ...
Page 66
ADAU1761 R19: ADC Control, 16,409 (0x4019) Bit 7 Bit 6 Bit 5 Reserved ADCPOL HPF Table 53. ADC Control Register Bits Bit Name Description 6 ADCPOL Invert input polarity normal (default inverted. 5 HPF ADC high-pass ...
Page 67
R21: Right Input Digital Volume, 16,411 (0x401B) Bit 7 Bit 6 Bit 5 Table 55. Right Input Digital Volume Register Bits Bit Name Description [7:0] RADVOL[7:0] Controls the digital volume attenuation for right channel inputs from either the right ADC ...
Page 68
ADAU1761 R23: Playback Mixer Left (Mixer 3) Control 1, 16,413 (0x401D) Bit 7 Bit 6 Bit 5 MX3G2[3:0] Table 57. Playback Mixer Left (Mixer 3) Control 1 Register Bits Bit Name Description [7:4] MX3G2[3:0] Bypass gain control. The signal from ...
Page 69
R24: Playback Mixer Right (Mixer 4) Control 0, 16,414 (0x401E) Bit 7 Bit 6 Bit 5 Reserved MX4RM MX4LM Table 58. Playback Mixer Right (Mixer 4) Control 0 Register Bits Bit Name Description 6 MX4RM Mixer input mute. Mutes the ...
Page 70
ADAU1761 R25: Playback Mixer Right (Mixer 4) Control 1, 16,415 (0x401F) Bit 7 Bit 6 Bit 5 MX4G2[3:0] Table 59. Playback Mixer Right (Mixer 4) Control 1 Register Bits Bit Name Description [7:4] MX4G2[3:0] Bypass gain control. The signal from ...
Page 71
R26: Playback L/R Mixer Left (Mixer 5) Line Output Control, 16,416 (0x4020) Bit 7 Bit 6 Bit 5 Reserved Table 60. Playback L/R Mixer Left (Mixer 5) Line Output Control Register Bits Bit Name Description [4:3] MX5G4[1:0] Mixer input gain ...
Page 72
ADAU1761 R28: Playback L/R Mixer Mono Output (Mixer 7) Control, 16,418 (0x4022) Bit 7 Bit 6 Bit 5 Reserved Table 62. Playback L/R Mixer Mono Output (Mixer 7) Control Register Bits Bit Name Description [2:1] MX7[1:0] L/R mono playback mixer ...
Page 73
R30: Playback Headphone Right Volume Control, 16,420 (0x4024) Bit 7 Bit 6 Bit 5 Table 64. Playback Headphone Right Volume Control Register Bits Bit Name Description [7:2] RHPVOL[5:0] Headphone volume control for right channel, RHP output. Each 1-bit step corresponds ...
Page 74
ADAU1761 R32: Playback Line Output Right Volume Control, 16,422 (0x4026) Bit 7 Bit 6 Bit 5 Table 66. Playback Line Output Right Volume Control Register Bits Bit Name Description [7:2] ROUTVOL[5:0] Line output volume control for right channel, ROUTN and ...
Page 75
R34: Playback Pop/Click Suppression, 16,424 (0x4028) Bit 7 Bit 6 Bit 5 Reserved Table 68. Playback Pop/Click Suppression Register Bits Bit Name Description 4 POPMODE Pop suppression circuit power saving mode. The pop suppression circuits charge faster in normal operation; ...
Page 76
ADAU1761 R36: DAC Control 0, 16,426 (0x402A) Bit 7 Bit 6 Bit 5 DACPOL DACMONO[1:0] Table 70. DAC Control 0 Register Bits Bit Name Description [7:6] DACMONO[1:0] DAC mono mode. The DAC channels can be set to mono mode within ...
Page 77
R38: DAC Control 2, 16,428 (0x402C) Bit 7 Bit 6 Bit 5 Table 72. DAC Control 2 Register Bits Bit Name Description [7:0] RDAVOL[7:0] Controls the digital volume attenuation for right channel inputs from the right DAC. Each bit corresponds ...
Page 78
ADAU1761 R40: Control Port Pad Control 0, 16,431 (0x402F) The optional pull-up/pull-down resistors are nominally 250 kΩ. When enabled, these pull-up/pull-down resistors set the control port signals to a defined state when the signal source becomes three-state. Bit 7 Bit ...
Page 79
R42: Jack Detect Pin Control, 16,433 (0x4031) With IOVDD set to 3.3 V, the low and high drive strengths of the JACKDET/MICIN pin are approximately 2.0 mA and 4.0 mA, respectively. With IOVDD set to 1.8 V, the low and ...
Page 80
ADAU1761 R43 to R47: Cyclic Redundancy Check Registers, 16,576 to 16,580 (0x40C0 to 0x40C4) The cyclic redundancy check (CRC) constantly checks the validity of the program RAM contents. SigmaStudio generates a 32-bit hash sum, which must be written to four ...
Page 81
R48 to R51: GPIO Pin Control, 16,582 to 16,585 (0x40C6 to 0x40C9) The GPIO pin control register sets the functionality of each GPIO pin as shown in Table 79. The GPIO functions use the same pins as the serial port ...
Page 82
ADAU1761 R52 to R56: Watchdog Registers, 16,592 to 16,596 (0x40D0 to 0x40D4) A program counter watchdog is used when the core does block processing (which can span several samples). The watchdog flags an error if the program counter reaches a ...
Page 83
R58: Serial Input Route Control, 16,626 (0x40F2) Bit 7 Bit 6 Bit 5 Reserved Table 83. Serial Input Route Control Register Bits Bit Name Description [3:0] SINRT[3:0] Serial data input routing. This register sets the input where the DACs receive ...
Page 84
ADAU1761 R60: Serial Data/GPIO Pin Configuration, 16,628 (0x40F4) The serial data/GPIO pin configuration register controls the functionality of the serial data port pins. If the bits in this register are set to 1, these pins are configured as GPIO interfaces ...
Page 85
R63: DSP Slew Modes, 16,631 (0x40F7) The DSP slew modes register sets the slew source for each output. The slew source can be either the DSP (digital slew) or the codec (analog slew). When these bits are set to Logic ...
Page 86
ADAU1761 R65: Clock Enable 0, 16,633 (0x40F9) This register disables or enables the digital clock engine for different blocks within the ADAU1761. For maximum power saving, use this register to disable blocks that are not being used. Bit 7 Bit ...
Page 87
Table 92. R8 and R9 Volume Settings Binary Value Volume Setting (dB) 000000 −12 000001 −11.25 000010 −10.5 000011 −9.75 000100 −9 000101 −8.25 000110 −7.5 000111 −6.75 001000 −6 001001 −5.25 001010 −4.5 001011 −3.75 001100 −3 001101 −2.25 ...
Page 88
ADAU1761 Table 94. R20, R21, R37, and R38 Volume Settings Binary Value Volume Attenuation (dB) 00000000 0 00000001 −0.375 00000010 −0.75 00000011 −1.125 00000100 −1.5 00000101 −1.875 00000110 −2.25 00000111 −2.625 00001000 −3 00001001 −3.375 00001010 −3.75 00001011 −4.125 00001100 ...
Page 89
Binary Value Volume Attenuation (dB) 01100000 −36 01100001 −36.375 01100010 −36.75 01100011 −37.125 01100100 −37.5 01100101 −37.875 01100110 −38.25 01100111 −38.625 01101000 −39 01101001 −39.375 01101010 −39.75 01101011 −40.125 01101100 −40.5 01101101 −40.875 01101110 −41.25 01101111 −41.625 01110000 −42 01110001 ...
Page 90
ADAU1761 Binary Value Volume Attenuation (dB) 11000010 −72.75 11000011 −73.125 11000100 −73.5 11000101 −73.875 11000110 −74.25 11000111 −74.625 11001000 −75 11001001 −75.375 11001010 −75.75 11001011 −76.125 11001100 −76.5 11001101 −76.875 11001110 −77.25 11001111 −77.625 11010000 −78 11010001 −78.375 11010010 −78.75 ...
Page 91
Binary Value Volume Setting (dB) 100001 −24 100010 −23 100011 −22 100100 −21 100101 −20 100110 −19 100111 −18 101000 −17 101001 −16 101010 −15 101011 −14 101100 −13 101101 −12 101110 −11 101111 −10 110000 −9 110001 −8 110010 ...
Page 92
... Temperature Range ADAU1761BCPZ −40°C to +85°C ADAU1761BCPZ-R7 −40°C to +85°C ADAU1761BCPZ-RL −40°C to +85°C EVAL-ADAU1761Z RoHS Compliant Part. ©2009–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 5.00 BSC SQ ...