A4989SLDTR-T Allegro Microsystems Inc, A4989SLDTR-T Datasheet - Page 12
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A4989SLDTR-T
Manufacturer Part Number
A4989SLDTR-T
Description
DUAL FULL BRDG MOSFET DRVR W/MICROSTEP TRANS
Manufacturer
Allegro Microsystems Inc
Datasheet
1.A4989SLDTR-T.pdf
(17 pages)
Specifications of A4989SLDTR-T
Applications
Stepper Motor Controller, 2-Phase
Number Of Outputs
1
Voltage - Load
12 V ~ 50 V
Voltage - Supply
3 V ~ 5.5 V
Operating Temperature
-20°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
38-TFSOP (0.173", 4.40mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Output
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
620-1389-2
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
A4989SLDTR-T
Manufacturer:
CDE
Quantity:
10 000
Part Number:
A4989SLDTR-T
Manufacturer:
ALLEGRO/雅丽高
Quantity:
20 000
A4989
in the phase to a desired value, I
of source and sink MOSFETs are enabled and current flows
through the motor winding and the current sense resistor,
RSENSEx. When the voltage across RSENSEx equals the
DAC output voltage, the current sense comparator resets
the PWM latch, which turns off the source MOSFET (slow
decay mode) or the sink and source MOSFETs (fast decay
mode). The maximum value of current limiting is set by the
selection of R
transconductance function approximated by:
The DAC, controlled by the translator, reduces the refer-
ence voltage, V
sinusoidal reference levels for the current sense comparator.
This limits the phase current trip level, I
the maximum current level, I
See table 3 for % I
Fixed Off-Time
circuitry uses the master oscillator to control the length of
time the power MOSFETs remain off. The off-time, t
is nominally 87 cycles of the master oscillator (21.75 μs at
4 MHz), but may be up to 1 cycle longer to synchronize with
the master oscillator.
Blanking
sense comparator when the outputs are switched by the
internal current control. The comparator output is blanked to
prevent false overcurrent detection due to reverse recovery
currents of the clamp diodes and switching transients related
to the capacitance of the load. The blank time, t
6 cycles of the master oscillator (1.5 μs at 4 MHz). Because
the t
error occurs.
Dead Time
in the power full-bridge, a dead time is introduced between
switching one MOSFET off and switching the complemen-
tary MOSFET on. The dead time, t
master oscillator (750 ns at 4MHz), but may be up to 1 cycle
longer to synchronize with the master oscillator.
BLANK
follows after the end of t
I
This function blanks the output of the current
TRIP
SENSE
To prevent cross-conduction (shoot through)
I
REF
TRIP(max)
= (% I
TRIP(max)
, in precise steps to produce the required
The internal PWM current control
and the voltage at the REF input, with a
TRIP(max)
= V
at each step.
REF
TRIP(max)
TRIP
/ (8 × R
/ 100) × I
DEAD
OFF
. Initially, a diagonal pair
, defined by:
, no synchronization
SENSE
TRIP
, is 3 cycles of the
TRIP(max)
, to a portion of
)
BLANK
OFF
, is
,
Dual Full-Bridge MOSFET Driver
ENABLE This input simply turns off all the power
MOSFETs. When set at logic high, the outputs are disabled.
When set at logic low, the internal control enables the out-
puts as required. Inputs to the translator (STEP, DIR, MS1,
and MS2) and the internal sequencing logic are all active
independent of the ENABLE input state.
RESET
power consumption when not in use. This disables much of
the internal circuitry, including the output MOSFETs and
internal regulator. When set at logic high, allows normal
operation and start-up of the device in the home position.
When coming out of sleep mode, wait 1 ms before issuing a
STEP command, to allow the internal regulator to stabilize.
The outputs can also be reset to the home position without
entering sleep mode. To do so, pulse the RESET input low,
with a pulse width between t
Mixed Decay Operation
Mixed decay is a technique that provides greater control
of phase currents while the current is decreasing. When a
stepper motor is driven at high speed, the back EMF from
the motor will lag behind the driving current. If a passive
current decay mode, such as slow decay, is used in the cur-
rent control scheme, then the motor back EMF can cause the
phase current to rise out of control. Mixed decay eliminates
this effect by putting the full-bridge initially into fast decay,
and then switching to slow decay after some time. Because
fast decay is an active (driven) decay mode, this portion of
the current decay cycle will ensure that the current remains
in control. Using fast decay for the full current decay time
(off-time) would result in a large ripple current, but switch-
ing to slow decay once the current is in control will reduce
the ripple current value. The portion of the off-time that the
full-bridge has to remain in fast decay will depend on the
characteristics and the speed of the motor.
When the magnitude of the phase current is rising, the motor
back EMF will not affect the current control and slow decay
may be used to minimize the phase current ripple. The
A4989 automatically switches between slow decay, when the
current is rising, and mixed decay, when the current magni-
tude is falling. The portion of the off-time that the full-bridge
remains in fast decay is defined by the PFD1 and PFD2
inputs. However, when high VBB voltages are used with
with Microstepping Translator
An active-low control input used to minimize
115 Northeast Cutoff
1.508.853.5000; www.allegromicro.com
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 U.S.A.
wR(min)
and t
wR(max)
.
12