AD1937WBSTZ Analog Devices Inc, AD1937WBSTZ Datasheet - Page 19

• Manufacturer Part Number: AD1937WBSTZ
• Description: 4ADCs/8DACs W/PLL 192 KHz, 24Bt Codec
• Manufacturer: Analog Devices Inc
• Type: General Purposer

Specifications of AD1937WBSTZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 4 / 8
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 96 / 96
• Dynamic Range, Adcs / Dacs (db) Typ: 105 / 110
• Voltage - Supply, Analog: 3 V ~ 3.6 V
• Voltage - Supply, Digital: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SERIAL DATA PORTS—DATA FORMAT
The eight DAC channels use a common serial bit clock (DBCLK)
and a common left-right framing clock (DLRCLK) in the serial
data port. The four ADC channels use a common serial bit
clock (ABCLK) and left-right framing clock (ALRCLK) in the
serial data port. The clock signals are all synchronous with the
sample rate. The normal stereo serial modes are shown in
Figure 15.
The ADC and DAC serial data modes default to I
The ports can also be programmed for left-justified stereo,
right-justified stereo, and TDM modes. The word width is
SDATA
SDATA
SDATA
SDATA
LRCLK
LRCLK
LRCLK
LRCLK
BCLK
BCLK
BCLK
BCLK
NOTES
1. DSP MODE DOES NOT IDENTIFY CHANNEL.
2. LRCLK NORMALLY OPERATES AT
3. BCLK FREQUENCY IS NORMALLY 64 × LRCLK BUT MAY BE OPERATED IN BURST MODE.
MSB
MSB
MSB
MSB
LEFT CHANNEL
LEFT CHANNEL
LEFT CHANNEL
f
S
RIGHT-JUSTIFIED MODE—SELECT NUMBER OF BITS PER CHANNEL
EXCEPT FOR DSP MODE, WHICH IS 2 ×
LEFT-JUSTIFIED MODE—16 BITS TO 24 BITS PER CHANNEL
I
2
S-JUSTIFIED MODE—16 BITS TO 24 BITS PER CHANNEL
LSB
2
S stereo.
DSP MODE—16 BITS TO 24 BITS PER CHANNEL
LSB
LSB
Figure 15. Stereo Modes
Rev. B | Page 19 of 36
LSB
1/
f
S
MSB
24 bits by default and can be set to 16 or 20 bits in the DAC
Control 2 and ADC Control 1 registers. The DAC serial formats
are programmable in the DAC Control 0 register. The polarity of
DBCLK and DLRCLK is programmable in the DAC Control 1 reg-
ister. The ADC serial format is programmable in ADC Control 1
register. The ABCLK and ALRCLK clock polarities are pro-
grammed in ADC Control 2 register. In Figure 2, Figure 3, and
Figure 15 all of the clocks are shown with their normal polarity.
Both DAC and ADC serial ports can be programmed to become
the bus masters according to DAC Control 1 and ADC Control 2
registers. By default, both ADC and DAC serial ports are in the
slave mode.
f
S
.
MSB
MSB
MSB
RIGHT CHANNEL
RIGHT CHANNEL
RIGHT CHANNEL
LSB
LSB
LSB
LSB
AD1937