AD1939WBSTZ-RL Analog Devices Inc, AD1939WBSTZ-RL Datasheet - Page 24
![no-image](/images/manufacturer_photos/0/0/57/analog_devices_inc_sml.jpg)
AD1939WBSTZ-RL
Manufacturer Part Number
AD1939WBSTZ-RL
Description
4-ADC 8-DAC Audio Codec W/on Chip PLL
Manufacturer
Analog Devices Inc
Type
General Purposer
Datasheet
1.AD1939YSTZ.pdf
(32 pages)
Specifications of AD1939WBSTZ-RL
Data Interface
Serial
Resolution (bits)
24 b
Number Of Adcs / Dacs
4 / 8
Sigma Delta
Yes
S/n Ratio, Adcs / Dacs (db) Typ
94 / 94
Dynamic Range, Adcs / Dacs (db) Typ
105 / 110
Voltage - Supply, Analog
3 V ~ 3.6 V
Voltage - Supply, Digital
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 105°C
Mounting Type
Surface Mount
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
AD1939
CONTROL REGISTERS
DEFINITIONS
The global address for the AD1939 is 0x04, shifted left one bit due to the R/ W bit. All registers are reset to 0, except for the DAC volume
registers that are set to full volume.
Note that the first setting in each control register parameter is the default setting.
Table 14. Register Format
Bit
Table 15. Register Addresses and Functions
Address
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PLL AND CLOCK CONTROL REGISTERS
Table 16. PLL and Clock Control 0 Register
Bit
0
2:1
4:3
6:5
7
Global Address
23:17
Value
0
1
00
01
10
11
00
01
10
11
00
01
10
11
0
1
Function
PLL and Clock Control 0
PLL and Clock Control 1
DAC Control 0
DAC Control 1
DAC Control 2
DAC individual channel mutes
DAC L1 volume control
DAC R1 volume control
DAC L2 volume control
DAC R2 volume control
DAC L3 volume control
DAC R3 volume control
DAC L4 volume control
DAC R4 volume control
ADC Control 0
ADC Control 1
ADC Control 2
Function
Normal operation
Power-down
INPUT 256 (× 44.1 kHz or 48 kHz)
INPUT 384 (× 44.1 kHz or 48 kHz)
INPUT 512 (× 44.1 kHz or 48 kHz)
INPUT 768 (× 44.1 kHz or 48 kHz)
XTAL oscillator enabled
256 × f
512 × f
Off
MCLKI/XI
DLRCLK
ALRCLK
Reserved
Disable: ADC and DAC idle
Enable: ADC and DAC active
S
S
VCO output
VCO output
R/W
16
Rev. C | Page 24 of 32
Description
PLL power-down
MCLKI/XI pin functionality (PLL active), master clock rate setting
MCLKO/XO pin, master clock rate setting
PLL input
Internal master clock enable
Register Address
15:8
Data
7:0