AD9268BCPZ-105 Analog Devices Inc, AD9268BCPZ-105 Datasheet - Page 12

• Manufacturer Part Number: AD9268BCPZ-105
• Description: Dual 16 Bit 105 High SNR ADC
• Manufacturer: Analog Devices Inc

Specifications of AD9268BCPZ-105

• Design Resources: Powering AD9268 with ADP2114 for Increased Efficiency (CN0137)
• Number Of Bits: 16
• Sampling Rate (per Second): 105M
• Data Interface: Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 590mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9268
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter
ELECTRICAL
ENVIRONMENTAL
1
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
The inputs and outputs are rated to the supply voltage (AVDD or ARVDD) +
0.2 V but should not exceed 2.1 V.
AVDD to AGND
DRVDD to AGND
VIN+A/VIN+B, VIN−A/VIN−B to AGND
CLK+, CLK− to AGND
SYNC to AGND
VREF to AGND
SENSE to AGND
VCM to AGND
RBIAS to AGND
CSB to AGND
SCLK/DFS to AGND
SDIO/DCS to AGND
OEB
PDWN
D0A/D0B through D15A/D15B to
DCOA/DCOB to AGND
Operating Temperature Range
Maximum Junction Temperature
Storage Temperature Range
AGND
(Ambient)
Under Bias
(Ambient)
1
Rating
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to DRVDD + 0.2 V
−0.3 V to DRVDD + 0.2 V
−0.3 V to DRVDD + 0.2 V
−0.3 V to DRVDD + 0.2 V
−0.3 V to DRVDD + 0.2 V
−0.3 V to DRVDD + 0.2 V
−0.3 V to DRVDD + 0.2 V
−40°C to +85°C
150°C
−65°C to +150°C
Rev. A | Page 12 of 44
THERMAL CHARACTERISTICS
The exposed paddle must be soldered to the ground plane for
the LFCSP package. Soldering the exposed paddle to the PCB
increases the reliability of the solder joints and maximizes the
thermal capability of the package.
Typical θ
plane. As shown in Table 7, airflow improves heat dissipation,
which reduces θ
package leads from metal traces, through holes, ground, and
power planes, reduces θ
Table 7. Thermal Resistance
Package Type
64-Lead LFCSP
(CP-64-6)
1
2
3
4
ESD CAUTION
Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
Per MIL-Std 883, Method 1012.1.
Per JEDEC JESD51-8 (still air).
Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board.
JA
is specified for a 4-layer PCB with a solid ground
JA
. In addition, metal in direct contact with the
Airflow
Velocity
(m/sec)
0
1.0
2.5
JA
.
θ
18.5
16.1
14.5
JA
1, 2
θ
1.0
JC
1, 3
θ
9.2
JB
1, 4
Unit
°C/W
°C/W
°C/W