AD9272BSVZ-40 Analog Devices Inc, AD9272BSVZ-40 Datasheet - Page 8
![12Bit 40 MSPS Octal ADC](/photos/6/60/66081/sv-100-3_sml.jpg)
AD9272BSVZ-40
Manufacturer Part Number
AD9272BSVZ-40
Description
12Bit 40 MSPS Octal ADC
Manufacturer
Analog Devices Inc
Type
Ultrasound Receiversr
Datasheet
1.AD9272BSVZ-80.pdf
(44 pages)
Specifications of AD9272BSVZ-40
Design Resources
Powering AD9272 with ADP5020 Switching Regulator PMU for Increased Efficiency (CN0135)
Resolution (bits)
12 b
Sampling Rate (per Second)
40M
Data Interface
Serial
Voltage Supply Source
Analog and Digital
Voltage - Supply
1.8V, 3V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AD9272-65EBZ - BOARD EVAL AD9272
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AD9272BSVZ-40
Manufacturer:
Analog Devices Inc
Quantity:
135
Company:
Part Number:
AD9272BSVZ-40
Manufacturer:
ADI
Quantity:
526
Company:
Part Number:
AD9272BSVZ-40
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
AD9272BSVZ-40
Manufacturer:
ADI/亚德诺
Quantity:
20 000
AD9272
DIGITAL SPECIFICATIONS
AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, f
Table 2.
Parameter
CLOCK INPUTS (CLK+, CLK−)
LOGIC INPUTS (PDWN, STBY, SCLK)
LOGIC INPUT (CSB)
LOGIC INPUT (SDIO)
LOGIC OUTPUT (SDIO)
DIGITAL OUTPUTS (DOUTx+, DOUTx−), IN ANSI-644 MODE
DIGITAL OUTPUTS (DOUTx+, DOUTx−), WITH
1
2
3
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were
completed.
Specified for LVDS and LVPECL only.
Specified for 13 SDIO pins sharing the same connection.
Logic Compliance
Differential Input Voltage
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
Logic 1 Voltage (I
Logic 0 Voltage (I
Logic Compliance
Differential Output Voltage (V
Output Offset Voltage (V
Output Coding (Default)
LOW POWER, REDUCED SIGNAL OPTION
Logic Compliance
Differential Output Voltage (V
Output Offset Voltage (V
Output Coding (Default)
1
OH
OL
= 50 μA)
= 800 μA)
3
OS
OS
2
)
)
OD
OD
)
)
1
1
Temperature
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
Full
Full
Full
Full
Rev. C | Page 8 of 44
Min
250
1.2
1.2
1.2
0
247
1.125
150
1.10
IN
= 5 MHz, full temperature, unless otherwise noted.
CMOS/LVDS/LVPECL
Typ
1.2
20
1.5
30
0.5
70
0.5
30
2
1.79
LVDS
Offset binary
LVDS
Offset binary
Max
3.6
0.3
3.6
0.3
DRVDD + 0.3
0.3
0.05
454
1.375
250
1.30
Unit
mV p-p
V
kΩ
pF
V
V
kΩ
pF
V
V
kΩ
pF
V
V
kΩ
pF
V
V
mV
V
mV
V