AD9516-4BCPZ Analog Devices Inc, AD9516-4BCPZ Datasheet - Page 14
![Clock IC With 1.8GHz On-chip VCO](/photos/6/50/65021/505-64-lfcsp_sml.jpg)
AD9516-4BCPZ
Manufacturer Part Number
AD9516-4BCPZ
Description
Clock IC With 1.8GHz On-chip VCO
Manufacturer
Analog Devices Inc
Type
Clock Generator, Fanout Distributionr
Datasheet
1.AD9516-4BCPZ.pdf
(80 pages)
Specifications of AD9516-4BCPZ
Pll
Yes
Input
Clock
Output
CMOS, LVDS, LVPECL
Number Of Circuits
1
Ratio - Input:output
1:14
Differential - Input:output
Yes/Yes
Frequency - Max
1.8GHz
Divider/multiplier
Yes/No
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LFCSP
Frequency-max
1.8GHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AD9516-4/PCBZ - BOARD EVAL FOR AD9516-4 1.8GHZ
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AD9516-4BCPZ
Manufacturer:
Analog Devices Inc
Quantity:
135
Company:
Part Number:
AD9516-4BCPZ
Manufacturer:
PROTEK
Quantity:
15 700
Company:
Part Number:
AD9516-4BCPZ
Manufacturer:
ADI
Quantity:
996
Part Number:
AD9516-4BCPZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
AD9516-4
POWER DISSIPATION
Table 17.
Parameter
POWER DISSIPATION, CHIP
POWER DELTAS, INDIVIDUAL FUNCTIONS
Power-On Default
Full Operation; CMOS Outputs at 229 MHz
Full Operation; LVDS Outputs at 200 MHz
PD Power-Down
PD Power-Down, Maximum Sleep
V
VCO Divider
REFIN (Differential)
REF1, REF2 (Single-Ended)
VCO
PLL
Channel Divider
LVPECL Channel (Divider Plus Output Driver)
LVPECL Driver
LVDS Channel (Divider Plus Output Driver)
LVDS Driver
CMOS Channel (Divider Plus Output Driver)
CMOS Driver (Second in Pair)
CMOS Driver (First in Second Pair)
Fine Delay Block
CP
Supply
Min
Typ
1.0
1.6
1.6
75
31
4
30
20
4
70
75
30
160
90
120
50
100
0
30
50
Rev. A | Page 14 of 80
Max
1.2
2.2
2.3
185
4.8
Unit
W
W
W
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
Test Conditions/Comments
No clock; no programming; default register values;
does not include power dissipated in external resistors
PLL on; internal VCO = 1625 MHz; VCO divider = 2;
all channel dividers on; six LVPECL outputs at 406 MHz;
eight CMOS outputs (10 pF load) at 203 MHz; all fine
delay on, maximum current; does not include power
dissipated in external resistors
PLL on; internal VCO = 1625 MHz, VCO divider = 2;
all channel dividers on; six LVPECL outputs at 406 MHz;
four LVDS outputs at 203 MHz; all fine delay on,
maximum current; does not include power dissipated
in external resistors
PD pin pulled low; does not include power dissipated
in terminations
PD pin pulled low; PLL power-down, Register 0x010[1:0] = 01b;
SYNC power-down, Register 0x230[2] = 1b; REF for
distribution power-down, Register 0x230[1] = 1b
PLL operating; typical closed loop configuration
Power delta when a function is enabled/disabled
VCO divider bypassed
All references off to differential reference enabled
All references off to REF1 or REF2 enabled; differential
reference not enabled
CLK input selected to VCO selected
PLL off to PLL on, normal operation; no reference enabled
Divider bypassed to divide-by-2 to divide-by-32
No LVPECL output on to one LVPECL output on,
independent of frequency
Second LVPECL output turned on, same channel
No LVDS output on to one LVDS output on; see Figure 8 for
dependence on output frequency
Second LVDS output turned on, same channel
Static; no CMOS output on to one CMOS output on; see
Figure 9 for variation over output frequency
Static; second CMOS output, same pair, turned on
Static; first output, second pair, turned on
Delay block off to delay block enabled; maximum
current setting