AD9516-4BCPZ-REEL7 Analog Devices Inc, AD9516-4BCPZ-REEL7 Datasheet - Page 11
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AD9516-4BCPZ-REEL7
Manufacturer Part Number
AD9516-4BCPZ-REEL7
Description
Clock IC With 1.8GHz On-chip VCO
Manufacturer
Analog Devices Inc
Type
Clock Generator, Fanout Distributionr
Datasheet
1.AD9516-4BCPZ.pdf
(80 pages)
Specifications of AD9516-4BCPZ-REEL7
Pll
Yes
Input
Clock
Output
CMOS, LVDS, LVPECL
Number Of Circuits
1
Ratio - Input:output
1:14
Differential - Input:output
Yes/Yes
Frequency - Max
1.8GHz
Divider/multiplier
Yes/No
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LFCSP
Frequency-max
1.8GHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AD9516-4/PCBZ - BOARD EVAL FOR AD9516-4 1.8GHZ
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER NOT USED)
Table 11.
Parameter
LVPECL OUTPUT ADDITIVE TIME JITTER
LVDS OUTPUT ADDITIVE TIME JITTER
CMOS OUTPUT ADDITIVE TIME JITTER
CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER USED)
Table 12.
Parameter
LVPECL OUTPUT ADDITIVE TIME JITTER
LVDS OUTPUT ADDITIVE TIME JITTER
CMOS OUTPUT ADDITIVE TIME JITTER
CLK = 622.08 MHz; LVPECL = 622.08 MHz; Divider = 1
CLK = 622.08 MHz; LVPECL = 155.52 MHz; Divider = 4
CLK = 1.6 GHz; LVPECL = 100 MHz; Divider = 16
CLK = 500 MHz; LVPECL = 100 MHz; Divider = 5
CLK = 1.6 GHz; LVDS = 800 MHz; Divider = 2;
CLK = 1 GHz; LVDS = 200 MHz; Divider = 5
CLK = 1.6 GHz; LVDS= 100 MHz; Divider = 16
CLK = 1.6 GHz; CMOS = 100 MHz; Divider = 16
CLK = 2.4 GHz; VCO DIV = 2; LVPECL = 100 MHz;
CLK = 2.4 GHz; VCO DIV = 2; LVDS = 100 MHz;
CLK = 2.4 GHz; VCO DIV = 2; CMOS = 100 MHz;
VCO Divider Not Used
Divider = 12; Duty-Cycle Correction = Off
Divider = 12; Duty-Cycle Correction = Off
Divider = 12; Duty-Cycle Correction = Off
Min
Min
Rev. A | Page 11 of 80
Typ
40
80
215
245
85
113
280
365
Typ
210
285
350
Max
Max
Unit
fs rms
fs rms
fs rms
fs rms
fs rms
fs rms
fs rms
fs rms
Unit
fs rms
fs rms
fs rms
Test Conditions/Comments
Distribution section only; does not include
PLL and VCO; uses rising edge of clock signal
BW = 12 kHz to 20 MHz
BW = 12 kHz to 20 MHz
Calculated from SNR of ADC method; DCC
not used for even divides
Calculated from SNR of ADC method;
DCC on
Distribution section only; does not include
PLL and VCO; uses rising edge of clock signal
BW = 12 kHz to 20 MHz
BW = 12 kHz to 20 MHz
Calculated from SNR of ADC method; DCC
not used for even divides
Distribution section only; does not include
PLL and VCO; uses rising edge of clock signal
Calculated from SNR of ADC method; DCC
not used for even divides
Test Conditions/Comments
Distribution section only; does not include
PLL and VCO; uses rising edge of clock signal
Calculated from SNR of ADC method
Distribution section only; does not include
PLL and VCO; uses rising edge of clock signal
Calculated from SNR of ADC method
Distribution section only; does not include
PLL and VCO; uses rising edge of clock signal
Calculated from SNR of ADC method
AD9516-4