AD9516-5/PCBZ Analog Devices Inc, AD9516-5/PCBZ Datasheet - Page 58
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AD9516-5/PCBZ
Manufacturer Part Number
AD9516-5/PCBZ
Description
Clock IC With 2.5GHz On-chip VCO EB
Manufacturer
Analog Devices Inc
Datasheet
1.AD9516-5BCPZ-REEL7.pdf
(76 pages)
Specifications of AD9516-5/PCBZ
Main Purpose
Timing, Clock Generator
Embedded
No
Utilized Ic / Part
AD9516-5
Primary Attributes
2 Inputs, 14 Outputs
Secondary Attributes
CMOS, LVDS, LVPECL Output Logic, ADIsimCLK™ Graphical User Interface
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Reg.
Addr
(Hex) Bit(s) Name
01A
01A
AD9516-5
[6]
[5:0] LD pin
Reference
frequency
monitor
threshold
control
Description
Sets the reference (REF1/REF2) frequency monitor’s detection threshold frequency. This does not affect
the CLK frequency monitor’s detection threshold (see Table 13, REF1, REF2, and CLK frequency status monitor).
[6] = 0; frequency valid if frequency is above the higher frequency threshold (default).
[6] = 1; frequency valid if frequency is above the lower frequency threshold.
Selects the LD pin signal.
[5]
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
[4]
0
0
0
0
0
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
[3]
0
0
0
0
0
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
[2]
0
0
0
0
1
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
[1]
0
0
1
1
0
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
[0]
0
1
0
1
0
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Rev. 0 | Page 58 of 76
LVL
Level or
Dynamic
Signal
DYN
DYN
HIZ
CUR
LVL
LVL
DYN
DYN
DYN
DYN
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
DYN
DYN
DYN
DYN
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
Digital lock detect (high = lock, low = unlock) (default).
P-channel, open-drain lock detect (analog lock detect).
N-channel, open-drain lock detect (analog lock detect).
High-Z LD pin.
Current source lock detect (110 μA when DLD is true).
Ground (dc); for all other cases of 0x0XXXX not specified.
Status of CLK frequency (active high).
Selected reference (low = REF1, high = REF2).
Digital lock detect (DLD); active high.
Holdover active (active high).
Status of REF1 frequency (active low).
Status of REF2 frequency (active low).
Selected reference (low = REF2, high = REF1).
Digital lock detect (DLD); active low.
Signal at LD Pin
The selections that follow are the same as REFMON.
Ground (dc).
REF1 clock (differential reference when in differential mode).
REF2 clock (N/A in differential mode).
Selected reference to PLL (differential reference when in
differential mode).
Unselected reference to PLL (not available in differential mode).
Status of selected reference (status of differential reference);
active high.
Status of unselected reference (not available in differential
mode); active high.
Status REF1 frequency (active high).
Status REF2 frequency (active high).
(Status REF1 frequency) AND (status REF2 frequency).
(DLD) AND (status of selected reference) AND (status of CLK).
N/A—do not use.
VS (PLL supply).
REF1 clock (differential reference when in differential mode).
REF2 clock (not available in differential mode).
Selected reference to PLL (differential reference when in
differential mode).
Unselected reference to PLL (not available when in differential
mode).
Status of selected reference (status of differential reference);
active low.
Status of unselected reference (not available in differential
mode); active low.
(Status of REF1 frequency) AND (Status of REF2 frequency).
(DLD) AND (Status of selected reference) AND (Status of CLK) .
Status of CLK frequency (active low).