AD9776ABSVZ Analog Devices Inc, AD9776ABSVZ Datasheet - Page 27
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AD9776ABSVZ
Manufacturer Part Number
AD9776ABSVZ
Description
IC,D/A CONVERTER,DUAL,12-BIT,CMOS,TQFP,100PIN
Manufacturer
Analog Devices Inc
Datasheet
1.AD9776ABSVZ.pdf
(60 pages)
Specifications of AD9776ABSVZ
Number Of Bits
12
Data Interface
Parallel
Number Of Converters
2
Voltage Supply Source
Analog and Digital
Power Dissipation (max)
300mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AD9776A-EBZ - BOARD EVALUATION AD9776A
Settling Time
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AD9776ABSVZ
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Company:
Part Number:
AD9776ABSVZRL
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Table 14. SPI Register Description
Register Name
Comm
Digital Control
Register
Address
0x00
0x00
0x00
0x00
0x00
0x00
0x01
0x01
0x01
0x01
0x02
0x02
0x02
0x02
0x02
0x02
0x02
0x02
Bits
7
6
5
4
3
1
7:6
5:2
1
0
7
6
5
4
3
2
1
0
Parameter
SDIO Bidirectional
LSB/MSB First
Software Reset
Power-Down Mode
Auto Power-Down Enable
PLL Lock Indicator
(Read Only)
Interpolation Factor<1:0>
Filter Modulation Mode<3:0>
DATACLK Delay<4>
Zero Stuffing Enable
Data Format
Interleaved Data Bus
Real Mode
DATACLK Delay Enable
Inverse Sinc Enable
DATACLK Invert
TxEnable Invert
Q First
Rev. A | Page 27 of 60
Function
0: use SDIO pin as input data only
1: use SDIO as both input and output data
0: first bit of serial data is MSB of data byte
1: first bit of serial data is LSB of data byte
Bit must be written with a 1, then 0 to soft reset SPI
register map.
0: all circuitry is active
1: disable all digital and analog circuitry, only SPI
port is active
Controls auto power-down mode. See the Power-
Down and Sleep Modes section.
0: PLL is not locked
1: PLL is locked
00: 1× interpolation
01: 2× interpolation
10: 4× interpolation
11: 8× interpolation
See Table 19 for filter modes.
Sets delay of REFCLK input to DATACLK output.
0: zero stuffing off
1: zero stuffing on
0: signed binary
1: unsigned binary
0: both P1D and P2D data ports enabled
1: data for both DACs received on P1D data port
0: enable Q path for signal processing
1: disable Q path data (internal Q channel clocks
disabled, I and Q modulators disabled)
Enables the DATACLK delay feature. More details
on this feature are shown in the Optimizing the
Data Input Timing section.
0: inverse sinc filter disabled
1: inverse sinc filter enabled
0: output DATACLK same phase as internal data
sampling clock, DCLK_SMP
1: output DATACLK opposite phase as internal data
sampling clock, DCLK_SMP
Inverts the polarity of Pin 39, the TXENABLE input
pin (also functions as IQSELECT).
0: in interleaved mode, the first byte of a data-word
pair is sent to the I DAC
1: in interleaved mode, the first byte of a data-word
pair is sent to the Q DAC
AD9776A/AD9778A/AD9779A
Default
0
0
0
0
00
0000
0
0
0
0
0
0
0
0