AD9777BSVZRL Analog Devices Inc, AD9777BSVZRL Datasheet - Page 50
![IC,D/A CONVERTER,DUAL,16-BIT,CMOS,TQFP,80PIN](/photos/6/64/66419/505-80-tqfp_sml.jpg)
AD9777BSVZRL
Manufacturer Part Number
AD9777BSVZRL
Description
IC,D/A CONVERTER,DUAL,16-BIT,CMOS,TQFP,80PIN
Manufacturer
Analog Devices Inc
Series
TxDAC+®r
Datasheet
1.AD9777BSVZ.pdf
(60 pages)
Specifications of AD9777BSVZRL
Settling Time
11ns
Number Of Bits
16
Data Interface
Parallel
Number Of Converters
2
Voltage Supply Source
Analog and Digital
Power Dissipation (max)
410mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AD9777-EBZ - BOARD EVALUATION FOR AD9777
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AD9777BSVZRL
Manufacturer:
Analog Devices Inc
Quantity:
10 000
AD9777
Figure 103. Test Configuration for AD9777 in Two-Port Mode with PLL Disabled, DAC Output Data Rate = Signal Generator Frequency,
Figure 104. Test Configuration for AD9777 in One-Port Mode with PLL Disabled, DAC Output Data Rate = Signal Generator Frequency,
ONEPORTCLK = Interleaved Input Data Rate = 2× Signal Generator Frequency/Interpolation Rate.
NOTES
1. TO USE PECL CLOCK DRIVER (U8), SOLDER JP41 AND JP42 AND REMOVE TRANSFORMER T1.
NOTES
1. TO USE PECL CLOCK DRIVER (U8), SOLDER JP41 AND JP42 AND REMOVE TRANSFORMER T1.
2. IN TWO-PORT MODE, IF DATACLK/PLL_LOCK IS PROGRAMMED TO OUTPUT PIN 8, JP25 AND
JP39 SHOULD BE SOLDERED. IF DATACLK/PLL_LOCK IS PROGRAMMED TO OUTPUT PIN 53,
JP46 AND JP47 SHOULD BE SOLDERED. SEE THE TWO PORT DATA INPUT MODE SECTION
FOR MORE INFORMATION.
INPUT CLOCK
INPUT CLOCK
JUMPER CONFIGURATION FOR TWO PORT MODE PLL OFF
JUMPER CONFIGURATION FOR ONE PORT MODE PLL OFF
JP12 –
JP24 –
JP25 –
JP26 –
JP27 –
JP31 –
JP32 –
JP33 –
JP12 –
JP24 –
JP25 –
JP26 –
JP27 –
JP31 –
JP32 –
JP33 –
AWG2021
JP1 –
JP2 –
JP3 –
JP5 –
JP6 –
AWG2021
JP1 –
JP2 –
JP3 –
JP5 –
JP6 –
DG2020
DG2020
OR
OR
DATACLK = Signal Generator Frequency/Interpolation Rate
SOLDERED/IN
SOLDERED/IN
LECROY
PULSE
GENERATOR
LECROY
PULSE
GENERATOR
×
×
×
×
×
40-PIN RIBBON CABLE
×
×
×
×
×
UNSOLDERED/OUT
UNSOLDERED/OUT
Rev. C | Page 50 of 60
TRIG
TRIG
INP
INP
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
DAC1, DB15–DB0
DAC2, DB15–DB0
ONEPORTCLK
DAC1, DB15–DB0
DAC2, DB15–DB0
DATACLK
SIGNAL GENERATOR
SIGNAL GENERATOR
CLK+/CLK–
CLK+/CLK–
AD9777
AD9777