ADE7758ARWZRL Analog Devices Inc, ADE7758ARWZRL Datasheet - Page 6
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ADE7758ARWZRL
Manufacturer Part Number
ADE7758ARWZRL
Description
IC,Power Metering,SOP,24PIN,PLASTIC
Manufacturer
Analog Devices Inc
Datasheet
1.ADE7758ARWZ.pdf
(72 pages)
Specifications of ADE7758ARWZRL
Input Impedance
380 KOhm
Measurement Error
0.1%
Voltage - I/o High
2.4V
Voltage - I/o Low
0.8V
Current - Supply
8mA
Voltage - Supply
4.75 V ~ 5.25 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
24-SOIC (0.300", 7.50mm Width)
Meter Type
3 Phase
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADE7758ARWZRL
Manufacturer:
ADI/亚德诺
Quantity:
20 000
ADE7758
Parameter
LOGIC OUTPUTS
POWER SUPPLY
1
2
3
TIMING CHARACTERISTICS
AVDD = DVDD = 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, CLKIN = 10 MHz XTAL, T
Table 2.
Parameter
WRITE TIMING
READ TIMING
1
2
3
4
5
See the Typical Performance Characteristics.
See the Terminology section for a definition of the parameters.
See the Analog Inputs section.
Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5 ns (10% to
90%) and timed from a voltage level of 1.6 V.
See the timing diagrams in Figure 3 and Figure 4 and the Serial Interface section.
Minimum time between read command and data read for all registers except waveform register, which is t
Measured with the load circuit in Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V.
Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted here is the true bus relinquish time of the part and is
independent of the bus loading.
IRQ, DOUT, and CLKOUT
APCF and VARCF
AVDD
DVDD
AI
DI
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
6
7
8
9
10
11
12
13
3
DD
DD
5
4
5
Output High Voltage, V
Output Low Voltage, V
Output High Voltage, V
Output Low Voltage, V
1, 2
1, 2
Specification
50
50
50
10
5
900
50
100
4
50
30
100
10
100
10
OL
OL
OH
OH
Unit
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
μs (min)
ns (min)
ns (min)
ns (max)
ns (min)
ns (max)
ns (min)
Test Conditions/Comments
CS falling edge to first SCLK falling edge
SCLK logic high pulse width
SCLK logic low pulse width
Valid data setup time before falling edge of SCLK
Data hold time after SCLK falling edge
Minimum time between the end of data byte transfers
Minimum time between byte transfers during a serial write
CS hold time after SCLK falling edge
Minimum time between read command (that is, a write to communication register) and
data read
Minimum time between data byte transfers during a multibyte read
Data access time after SCLK rising edge following a write to the communications register
Bus relinquish time after falling edge of SCLK
Bus relinquish time after rising edge of CS
Specification
4
0.4
4
1
4.75
5.25
4.75
5.25
8
13
Rev. D | Page 6 of 72
Unit
V min
V max
V min
V max
V min
V max
V min
V max
mA max
mA max
Test Conditions/Comments
DVDD = 5 V ± 5%
IRQ is open-drain, 10 kΩ pull-up resistor
I
I
I
I
For specified performance
5 V − 5%
5 V + 5%
5 V − 5%
5 V + 5%
Typically 5 mA
Typically 9 mA
SOURCE
SINK
SOURCE
SINK
= 1 mA
= 5 mA
9
= 500 ns min.
= 5 mA
= 8 mA
MIN
to T
MAX
= −40°C to +85°C.