ADSP-21266SKSTZ-2D Analog Devices Inc, ADSP-21266SKSTZ-2D Datasheet - Page 26

• Manufacturer Part Number: ADSP-21266SKSTZ-2D
• Description: IC,DSP,32-BIT,CMOS,QFP,144PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of ADSP-21266SKSTZ-2D

• Interface: DAI, SPI
• Clock Rate: 200MHz
• Non-volatile Memory: ROM (512 kB)
• On-chip Ram: 256kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 32b
• Architecture: Super Harvard
• Format: Floating Point
• Clock Freq (max): 200MHz
• Mips: 200
• Device Input Clock Speed: 200MHz
• Ram Size: 256KB
• Program Memory Size: 512KB
• Operating Supply Voltage (typ): 1.2/3.3V
• Operating Supply Voltage (min): 1.14/3.13V
• Operating Supply Voltage (max): 1.26/3.47V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-21266
Table 23. 16-Bit Memory Read Cycle
1
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
t
t
D = (The value set by the PPDUR Bits (5–1) in the PPCTL register) × t
H = t
On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low.
DRS
DRH
ALEW
ALERW
ADAS
ADAH
ALEHZ
RW
1
1
CCLK
1
(if a hold cycle is specified, else H = 0)
Address/Data 15–0 Setup Before RD high
Address/Data 15–0 Hold After RD high
ALE Pulse Width
ALE Deasserted to Read/Write Asserted
Address/Data 15–0 Setup Before ALE Deasserted
Address/Data 15–0 Hold After ALE Deaserted
ALE Deasserted to Address/Data 15–0 in High-Z
RD Pulse Width
AD15-0
ALE
WR
RD
VALID ADDRESS
t
ADAS
t
ALEW
Rev. C | Page 26 of 44 | October 2007
Figure 19. 16-Bit Memory Read Cycle
t
ADAH
t
t
ALERW
ALEHZ
CCLK
t
RW
t
VALID DATA
DRS
Min
3.3
0
2 × t
1 × t
2.5 × t
0.5 × t
0.5 × t
D – 2
CCLK
CCLK
CCLK
CCLK
CCLK
t
DRH
– 2
– 0.5
– 2.0
– 0.8
– 0.8
Max
0.5 × t
CCLK
+ 2.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns