ADUC7034BCPZ-RL Analog Devices Inc, ADUC7034BCPZ-RL Datasheet - Page 57

• Manufacturer Part Number: ADUC7034BCPZ-RL
• Description: IC,Battery Management,LLCC,48PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7034BCPZ-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 115°C
• Package / Case: 48-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

In ADC normal power mode, the maximum ADC throughput
rate is 8 kHz. This is configured by setting the SF and AF bits in
the ADCFLT MMR to 0 with all other filtering options disabled.
As a result, 0x0000 is written to ADCFLT. Figure 23 shows a
typical 8 kHz filter response based on these settings.
A modified version of the 8 kHz filter response can be configured
by setting the running average bit (ADCFLT[14]). As a result,
an additional running-average-by-two filter is introduced on all
ADC output samples, which further reduces the ADC output
noise. In addition, by maintaining an 8 kHz ADC throughput
rate, the ADC settling time is increased by one full conversion
period. The modified frequency response for this configuration
is shown in Figure 24.
Figure 23. Typical Digital Filter Response at f
–100
Figure 22. Modified Sinc3 Digital Filter Response at f
–100
–10
–20
–30
–40
–50
–60
–70
–80
–90
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
0
0
0
0.5
2
4
1.0
6
1.5
(ADCFLT = 0x0087)
8
FREQUENCY (kHz)
FREQUENCY (kHz)
2.0
10
2.5
12
14
3.0
ADC
= 8 kHz (ADCFLT = 0x0000)
16
3.5
18
4.0
ADC
20
4.5
= 1 kHz
22
5.0
24
Rev. B | Page 57 of 136
At very low throughput rates, the chop bit in the ADCFLT
register can be enabled to minimize offset errors and, more
importantly, temperature drift in the ADC offset error. With
chop enabled, there are two primary variables (sinc3 decimation
factor and averaging factor) available to allow the user to select
an optimum filter response, but there is a trade-off between
filter bandwidth and ADC noise.
For example, with the chop enable bit (ADCFLT[15]) set to 1,
the SF value (ADCFLT[6:0]) increases to 0x1F (31 decimal) and
an AF value (ADCFLT[13:8]) of 0x16 (22 decimal) is selected,
resulting in an ADC throughput of 10 Hz. The frequency
response in this case is shown in Figure 25.
Changing SF to 0x1D and setting AF to 0x3F with the chop bit
still enabled configures the ADC with its minimum throughput
rate of 4 Hz in normal mode. The digital filter frequency response
with this configuration is shown in Figure 26.
Figure 24. Typical Digital Filter Response at f
Figure 25. Typical Digital Filter Response at f
–100
–100
–10
–20
–30
–40
–50
–60
–70
–80
–90
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
0
0
0
2
20
4
40
6
60
8
FREQUENCY (kHz)
FREQUENCY (kHz)
80
10
100
12
14
120
ADC
ADC
= 8 kHz (ADCFLT = 0x4000)
= 10 Hz (ADCFLT = 0x961F)
16
140
18
160
ADuC7034
20
180
22
200
24