ADUC7039BCP6Z-RL Analog Devices Inc, ADUC7039BCP6Z-RL Datasheet - Page 25

• Manufacturer Part Number: ADUC7039BCP6Z-RL
• Description: Flash 64k ARM7 Dual 16-Bit ADC LIN I.C.
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7039BCP6Z-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI
• Peripherals: POR, Temp Sensor, WDT
• Number Of I /o: 6
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 115°C
• Package / Case: 32-LFCSP
• Lead Free Status / RoHS Status: Lead free by exemption / RoHS compliant by exemption
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free by exemption / RoHS compliant by exemption

MEMORY MAPPED REGISTERS (MMR)
The memory mapped register (MMR) space is mapped into
the top 4 kB of the MCU memory space and accessed by
indirect addressing, load, and store commands through the
ARM7 banked registers. An outline of the memory mapped
register bank for the ADuC7039 is shown in Figure 10.
The MMR space provides an interface between the CPU and
all on-chip peripherals. All registers except the ARM7 core
registers (described in the ARM Registers section) reside in
the MMR area.
As shown in the detailed MMR maps in the Complete MMR
Listing section (Table 14 to Table 23), the MMR data widths
vary from 1 byte (8 bits) to 4 bytes (32 bits). The ARM7 core
can access any of the MMRs (single byte or multiple byte width
registers) with a 32-bit read or write access.
The resultant read, for example, is aligned per little endian
format as previously described in this data sheet. However,
errors result if the ARM7 core tries to access 4-byte (32-bit)
MMRs with a 16-bit access. In the case of a (16-bit) write
access to a 32-bit MMR, the (upper) 16 most significant
bits are written as 0s. More obviously, in the case of a
16-bit read access to a 32-bit MMR, only 16 of the MMR
bits can be read.
Rev. B | Page 25 of 92
0xFFFFFFFF
0xFFFF0D20
0xFFFF0D00
0xFFFF0A14
0xFFFF0A00
0xFFFF04A4
0xFFFF0E24
0xFFFF0E00
0xFFFF0810
0xFFFF0804
0xFFFF0800
0xFFFF0700
0xFFFF0560
0xFFFF0500
0xFFFF0400
0xFFFF0350
0xFFFF0340
0xFFFF0334
0xFFFF0320
0xFFFF0310
0xFFFF0300
0xFFFF0248
0xFFFF0220
0xFFFF0110
0xFFFF0000
Figure 10. Top Level MMR Map
OSCILLATOR CONTROL
SYSTEM CONTROL
FLASH CONTROL
CONTROLLER
REMAP AND
HARDWARE
WATCHDOG
INTERFACE
INTERFACE
INTERRUPT
WAKE-UP
PLL AND
TIMER 2
TIMER 1
TIMER 0
GPIO
ADC
SPI
LIN
HV
ADuC7039