ADUC7128BCPZ126-RL Analog Devices Inc, ADUC7128BCPZ126-RL Datasheet - Page 60

• Manufacturer Part Number: ADUC7128BCPZ126-RL
• Description: IC,MICROCONTROLLER,16-BIT,ARM7 CPU,LLCC,64PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7128BCPZ126-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 41.78MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: PLA, POR, PWM, PSM, Temp Sensor, WDT
• Number Of I /o: 28
• Program Memory Size: 126KB (126K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x12b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADUC7128QSPZ - KIT DEV FOR ADUC7128
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADUC7128BCPZ126-RLTR

ADuC7128/ADuC7129
Table 82. COMxIEN0 MMR Bit Designations
Bit
7:4
3
2
1
0
Table 83. COMxIID0 MMR Bit Designations
Bit 2:1
Status Bits
00
11
10
01
00
Table 84. COMxCON1 MMR Bit Designations
Bit
7:5
4
3
2
1
0
Name
RSVD
ETBEI
Name
RSVD
LOOPBACK
RTS
DTR
EDSSI
ELSI
ERBFI
Bit 0
NINT
1
0
0
0
0
Description
Reserved.
Loop Back.
Reserved.
Reserved.
Request to Send.
Data Terminal Ready.
Description
Reserved.
Modem Status Interrupt Enable Bit.
RX Status Interrupt Enable Bit.
Enable Transmit Buffer Empty Interrupt.
Enable Receive Buffer Full Interrupt.
Priority
1
2
3
4
Set by user to enable loop-back mode. In loop-back mode, the SOUT is forced high. In addition, the modem
signals are directly connected to the status inputs (RTS to CTS, DTR to DSR, OUT1 to RI, and OUT2 to DCD).
Set by user to force the RTS output to 0.
Cleared by user to force the RTS output to 1.
Set by user to force the DTR output to 0.
Cleared by user to force the DTR output to 1.
Set by user to enable generation of an interrupt if any of COMxSTA1[3:0] are set.
Cleared by user.
Set by user to enable generation of an interrupt if any of COMxSTA0[3:1] are set.
Cleared by user.
Set by user to enable interrupt when buffer is empty during a transmission.
Cleared by user.
Set by user to enable interrupt when buffer is full during a reception.
Cleared by user.
No Interrupt.
Receive Line Status Interrupt.
Receive Buffer Full Interrupt.
Modem Status Interrupt.
Definition
Transmit Buffer Empty Interrupt.
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Clearing Operation
Read COMxSTA0.
Read COMxRX.
Write data to COMxTX or read COMxIID0.
Read COMxSTA1.