AM29LV800BT-70EI AMD (ADVANCED MICRO DEVICES), AM29LV800BT-70EI Datasheet - Page 14

• Manufacturer Part Number: AM29LV800BT-70EI
• Description: IC 8M FLSH (512KX16) TOP SECTO
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

The device features an Unlock Bypass mode to facil-
itate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are
required to program a word or byte, instead of four.
The “Word/Byte Program Command Sequence”
section has details on programming data to the
device using both standard and Unlock Bypass
command sequences.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. Tables 2 and 3 indicate the
address space that each sector occupies. A “sector
address” consists of the address bits required to
uniquely select a sector. The “Command Definitions”
section has details on erasing a sector or the entire
chip, or suspending/resuming the erase operation.
After the system writes the autoselect command
sequence, the device enters the autoselect mode.
The system can then read autoselect codes from the
internal register (which is separate from the memory
array) on DQ7–DQ0. Standard read cycle timings
apply in this mode. Refer to the “Autoselect Mode”
and “Autoselect Command Sequence” sections for
more information.
I
active current specification for the write mode. The
“AC Characteristics” section contains timing specifica-
tion tables and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system
may check the status of the operation by reading the
status bits on DQ7–DQ0. Standard read cycle timings
and I
Operation Status” for more information, and to “AC
Characteristics” for timing diagrams.
Standby Mode
When the system is not reading or writing to the
device, it can place the device in the standby mode.
In this mode, current consumption is greatly reduced,
and the outputs are placed in the high impedance
state, independent of the OE# input.
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at V
(Note that this is a more restricted voltage range than
V
within V
mode, but the standby current will be greater. The
device requires standard access time (t
access when the device is in either of these standby
modes, before it is ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
12
CC2
IH
.) If CE# and RESET# are held at V
in the DC Characteristics table represents the
CC
CC
read specifications apply. Refer to “Write
± 0.3 V, the device will be in the standby
CE
IH
CC
) for read
, but not
± 0.3 V.
Am29LV800B
In the DC Characteristics table, I
sents the standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device
energy consumption. The device automatically
enables this mode when addresses remain stable for
t
dent of the CE#, WE#, and OE# control signals. Stan-
dard address access timings provide new data when
addresses are changed. While in sleep mode, output
data is latched and always available to the system.
I
automatic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of
resetting the device to reading array data. When the
RESET# pin is driven low for at least a period of t
the device immediately terminates any operation
in progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state
machine to reading array data. The operation that
was interrupted should be reinitiated once the device
is ready to accept another command sequence, to
ensure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
draws CMOS standby current (I
held at V
current will be greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up
firmware from the Flash memory.
If RESET# is asserted during a program or erase
operation, the RY/BY# pin remains a “0” (busy) until
the internal reset operation is complete, which
requires a time of t
rithms). The system can thus monitor RY/BY# to
determine whether the reset operation is complete. If
RESET# is asserted when a program or erase opera-
tion is not executing (RY/BY# pin is “1”), the reset
operation is completed within a time of t
during Embedded Algorithms). The system can read
data t
Refer to the AC Characteristics tables for RESET#
parameters and to Figure 14 for the timing diagram.
Output Disable Mode
ACC
CC4
+ 30 ns. The automatic sleep mode is indepen-
in the DC Characteristics table represents the
RH
after the RESET# pin returns to V
IL
but not within V
READY
(during Embedded Algo-
SS
±0.3 V, the standby
SS
CC4
CC3
±0.3 V, the device
). If RESET# is
and I
READY
IH
CC4
.
repre-
(not
RP
,