CY7C025E-25AXC Cypress Semiconductor Corp, CY7C025E-25AXC Datasheet - Page 14

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CY7C025E-25AXC

Manufacturer Part Number
CY7C025E-25AXC
Description
CY7C025E-25AXC
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C025E-25AXC

Format - Memory
RAM
Memory Type
SRAM - Dual Port, Asynchronous
Memory Size
128K (8K x 16)
Speed
25ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
428-3072

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C025E-25AXC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Part Number:
CY7C025E-25AXCT
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Switching Waveforms
Notes
Document Number: 001-62932 Rev. *A
35. R/W must be HIGH during all address transitions.
36. A write occurs during the overlap (t
37. t
38. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
39. To access RAM, CE = V
40. To access upper byte, CE = V
41. Transition is measured ±500 mV from steady state with a 5 pF load (including scope and jig). This parameter is sampled and not 100% tested.
42. During this period, the I/O pins are in the output state, and input signals must not be applied.
43. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high impedance state.
CE
DATA OUT
ADDRESS
ADDRESS
CE
placed on the bus for the required t
the specified t
To access lower byte, CE = V
HA
DATA IN
DATA IN
[39,40]
is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
[39,40]
R/W
R/W
OE
PWE
.
IL
, SEM = V
IL
, LB = V
IL
, UB = V
t
t
SA
SA
IH
NOTE 42
SD
Figure 7. Write Cycle No. 1: R/W Controlled Timing
SCE
IL
Figure 8. Write Cycle No. 2: CE Controlled Timing
.
(continued)
, SEM = V
. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as
IL
or t
, SEM = V
PWE
) of a LOW CE or SEM and a LOW UB or LB.
IH
.
IH
.
t
HZWE
[41]
t
t
AW
AW
t
t
WC
WC
t
t
SCE
PWE
[38]
t
t
SD
SD
PWE
or (t
HZWE
t
t
HA
HA
[35, 36, 37, 43]
+ t
[35, 36, 37, 38 ]
SD
t
t
HD
HD
) to allow the I/O drivers to turn off and data to be
t
LZWE
CY7C024E, CY7C0241E
CY7C025E, CY7C0251E
t
HZOE
NOTE 42
[41]
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