CY8CTMG201A-32LQXI Cypress Semiconductor Corp, CY8CTMG201A-32LQXI Datasheet - Page 238
CY8CTMG201A-32LQXI
Manufacturer Part Number
CY8CTMG201A-32LQXI
Description
CY8CTMG201A-32LQXI
Manufacturer
Cypress Semiconductor Corp
Series
TrueTouch™r
Datasheet
1.CY8CTST200-16LGXI.pdf
(308 pages)
Specifications of CY8CTMG201A-32LQXI
Applications
Touchscreen Controller
Core Processor
M8C
Program Memory Type
FLASH (16 kB)
Controller Series
CY8CT
Ram Size
2K x 8
Interface
I²C, SPI, UART/USART, USB
Number Of I /o
28
Voltage - Supply
1.8 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
*
Package / Case
*
Processor Series
CY8CTxx2xxA
Core
M8C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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MVW_PP
21.3.50 MVW_PP
This register is used to set the effective SRAM page for MVI write memory accesses in a multi-SRAM page PSoC device.
This register is only used when a device has more than one page of SRAM. In the table above, note that reserved bits are
grayed table cells and are not described in the bit description section below. Reserved bits must always be written with a
value of ‘0’. For additional information, refer to the
Bit
2:0
238
Individual Register Names and Addresses:
MVW_PP : 0,D5h
Access : POR
Bit Name
0,D5h
Page Bits[2:0]
Name
MVI Write Page Pointer Register
7
6
Description
Bits determine which SRAM page an MVI Write instruction operates on.
000b
001b
010b
011b
100b
101b
110b
111b
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
SRAM Page 0
SRAM Page 1
SRAM Page 2
SRAM Page 3
SRAM Page 4
SRAM Page 5
SRAM Page 6
SRAM Page 7
5
0,D5h
Register Definitions on page 42
4
3
in the RAM Paging chapter .
2
Page Bits[2:0]
RW : 0
1
0
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