CY8CTMG201A-32LQXI Cypress Semiconductor Corp, CY8CTMG201A-32LQXI Datasheet - Page 284
CY8CTMG201A-32LQXI
Manufacturer Part Number
CY8CTMG201A-32LQXI
Description
CY8CTMG201A-32LQXI
Manufacturer
Cypress Semiconductor Corp
Series
TrueTouch™r
Datasheet
1.CY8CTST200-16LGXI.pdf
(308 pages)
Specifications of CY8CTMG201A-32LQXI
Applications
Touchscreen Controller
Core Processor
M8C
Program Memory Type
FLASH (16 kB)
Controller Series
CY8CT
Ram Size
2K x 8
Interface
I²C, SPI, UART/USART, USB
Number Of I /o
28
Voltage - Supply
1.8 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
*
Package / Case
*
Processor Series
CY8CTxx2xxA
Core
M8C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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SLP_CFG2
21.4.25 SLP_CFG2
This register holds the configuration for I2C sleep, deep sleep, and buzz.
In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below.
Reserved bits must always be written with a value of ‘0’. For additional information, refer to the
page 77
Bit
3:2
1
0
284
Individual Register Names and Addresses:
SLP_CFG2 : 1,ECh
Access : POR
Bit Name
1,ECh
in the Sleep and Watchdog chapter.
ALT_Buzz[1:0]
I2C_ON
LSO_OFF
Name
Sleep Configuration Register 2
7
6
Description
These bits control additional selections for POR/LVD buzz rates.
00
01
10
11
This bit enables the standby regulator in I2C sleep mode at a level sufficient to supply the I2C cir-
cuitry.
This bit disables the LSO oscillator when in sleep state.
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Compatibility mode, buzz rate is determined by PSSDC bits.
Duty cycle is 1/32768.
Duty cycle is 1/8192.
Reserved.
5
4
3
ALT_Buzz[1:0]
RW : 0
2
1,ECh
I2C_ON
Register Definitions on
RW : 0
1
LSO_OFF
RW : 0
0
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