CY8CTMG201A-32LQXIT Cypress Semiconductor Corp, CY8CTMG201A-32LQXIT Datasheet - Page 75
CY8CTMG201A-32LQXIT
Manufacturer Part Number
CY8CTMG201A-32LQXIT
Description
CY8CTMG201A-32LQXIT
Manufacturer
Cypress Semiconductor Corp
Series
TrueTouch™r
Datasheet
1.CY8CTST200-16LGXI.pdf
(308 pages)
Specifications of CY8CTMG201A-32LQXIT
Applications
Touchscreen Controller
Core Processor
M8C
Program Memory Type
FLASH (16 kB)
Controller Series
CY8CT
Ram Size
2K x 8
Interface
I²C, SPI, UART/USART, USB
Number Of I /o
28
Voltage - Supply
1.8 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
32-UQFN Exposed Pad, 32-HUQFN, 32-SQFN
Processor Series
CY8CTxx2xxA
Core
M8C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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As shown in
timing diagram. The taps used in this wakeup sequence are generated based upon user configuration settings in the
SLP_CFG3 register.”
1. The duration of Power Good is 3 ILO Cycles.
2. The timing of T0 – T4 is based on the IMO frequency and the settings in the SLP_CFG3 register. For additional information, refer to the
3. The maximum worst-case duration of the wakeup sequence is 263 µs, based on the minimum specified ILO frequency of 19 kHz, the minimum specified IMO
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Switch reference
from standby to
on page
frequency, and the default settings of the SLP_CFG3 register.
Regulator Enable
Bandgap Enable
Power switches
Enable Flash
Sample Bandgap
Idle_Flash
POR Enable
IMO Enable
Enable
BG
Sample POR
78.
SLEEP
PD
Figure
BRQ
INT
10-2, once the SLEEP bit is deasserted, the wakeup is initiated. The sequence is shown in the following
Interrupt
Power good
Figure 10-2. Wakeup Sequence for the Device
T0
10 – 60 µs
T1
3 – 20 µs
123
T2
½ CPU
clock
cycle
T3
Sleep and Watchdog
1 – 20 µs
SLP_CFG3 Register
T4
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