DSPIC33FJ32GS606-E/MR Microchip Technology, DSPIC33FJ32GS606-E/MR Datasheet - Page 238
DSPIC33FJ32GS606-E/MR
Manufacturer Part Number
DSPIC33FJ32GS606-E/MR
Description
16 Bit MCU/DSP 40MIPS 32KB FLASH 64 QFN 9x9x0.9mm TUBE
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheet
1.DSPIC33FJ32GS406-IPT.pdf
(418 pages)
Specifications of DSPIC33FJ32GS606-E/MR
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, QEI, POR, PWM, WDT
Number Of I /o
58
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
64-VFQFN, Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
REGISTER 16-11: PWMCONx: PWM CONTROL REGISTER (CONTINUED)
DS70591C-page 238
bit 8
bit 7-6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1: Software must clear the interrupt status here, and in the corresponding IFS bit in the Interrupt Controller.
2: The Independent Time Base mode (ITB = 1) must be enabled to use Center-Aligned mode. If ITB = 0, the
3: These bits should not be changed after the PWM is enabled (PTEN = 1) (PTCON<15>).
4: For DTCP to be effective, DTC<1:0> must be set to ‘11’; otherwise, DTCP is ignored.
5: Center-Aligned mode ignores the least significant 3 bits of the duty cycle, phase, and dead time registers.
6: Configure CLMOD = 0 (FCLCONX<8>) and ITB = 1 (PWMCONx<9>) to operate in External Period Reset
CAM bit is ignored.
The highest Center-Aligned mode resolution available is 8.32 ns with the clock prescaler set to the fastest
clock.
mode.
MDCS: Master Duty Cycle Register Select bit
1 = MDC register provides duty cycle information for this PWM generator
0 = PDCx and SDCx registers provide duty cycle information for this PWM generator
DTC<1:0>: Dead Time Control bits
11 = Dead Time Compensation mode
10 = Dead time function is disabled
01 = Negative dead time actively applied for Complementary Output mode
00 = Positive dead time actively applied for all output modes
DTCP: Dead Time Compensation Polarity bit
1 = If DTCMPx = 0, PWMxL is shortened, and PWMxH is lengthened
0 = If DTCMPx = 0, PWMxH is shortened, and PWMLx is lengthened
Unimplemented: Read as ‘0’
MTBS: Master Time Base Select bit
1 = PWM generator uses the secondary master time base for synchronization and the clock source
0 = PWM generator uses the primary master time base for synchronization and the clock source for
CAM: Center-Aligned Mode Enable bit
1 = Center-Aligned mode is enabled
0 = Edge-Aligned mode is enabled
XPRES: External PWM Reset Control bit
1 = Current-limit source resets the time base for this PWM generator if it is in Independent Time Base
0 = External pins do not affect PWM time base
IUE: Immediate Update Enable bit
1 = Updates to the active MDC/PDCx/SDCx registers are immediate
0 = Updates to the active PDCx registers are synchronized to the PWM time base
mode
If DTCMPx = 1, PWMxH is shortened, and PWMxL is lengthened
If DTCMPx = 1, PWMxL is shortened, and PWMxH is lengthened
for the PWM generation logic (if secondary time base is available)
the PWM generation logic
Preliminary
(2,3,5)
(6)
(4)
(3)
2010 Microchip Technology Inc.
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