EP20K600EFC672-2X Altera, EP20K600EFC672-2X Datasheet
EP20K600EFC672-2X
Manufacturer Part Number
EP20K600EFC672-2X
Description
APEX 20KE
Manufacturer
Altera
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Features
Altera Corporation
DS-APEX20K-5.1
Maximum
system
gates
Typical
gates
LEs
ESBs
Maximum
RAM bits
Maximum
macrocells
Maximum
user I/O
pins
March 2004, ver. 5.1
Table 1. APEX 20K Device Features
Feature
EP20K30E
113,000
30,000
24,576
1,200
192
128
12
EP20K60E
162,000
■
■
60,000
32,768
2,560
256
196
16
Industry’s first programmable logic device (PLD) incorporating
system-on-a-programmable-chip (SOPC) integration
–
–
–
–
High density
–
–
–
–
MultiCore
product-term logic, and embedded memory
LUT logic used for register-intensive functions
Embedded system block (ESB) used to implement memory
functions, including first-in first-out (FIFO) buffers, dual-port
RAM, and content-addressable memory (CAM)
ESB implementation of product-term logic used for
combinatorial-intensive functions
30,000 to 1.5 million typical gates (see
Up to 51,840 logic elements (LEs)
Up to 442,368 RAM bits that can be used without reducing
available logic
Up to 3,456 product-term-based macrocells
Note (1)
EP20K100
263,000
100,000
53,248
4,160
416
252
26
TM
architecture integrating look-up table (LUT) logic,
EP20K100E EP20K160E
263,000
100,000
53,248
4,160
416
246
26
404,000
160,000
81,920
6,400
640
316
40
Programmable Logic
Tables 1
EP20K200
526,000
200,000
106,496
8,320
832
382
52
Device Family
APEX 20K
and 2)
EP20K200E
Data Sheet
526,000
200,000
106,496
8,320
832
376
52
1
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