EVAL-AD5560EBUZ Analog Devices Inc, EVAL-AD5560EBUZ Datasheet
EVAL-AD5560EBUZ
Specifications of EVAL-AD5560EBUZ
Related parts for EVAL-AD5560EBUZ
EVAL-AD5560EBUZ Summary of contents
Page 1
FEATURES Programmable device power supply (DPS) FV, MI, MV, FNMV functions 5 internal current ranges (on-chip R SENSE ±5 μA, ±25 μA, ±250 μA, ±2.5 mA, ± external high current ranges (external R EXTFORCE1: ±1.2 A maximum EXTFORCE2: ...
Page 2
AD5560 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Revision History ............................................................................... 3 Functional Block Diagram .............................................................. 4 Specifications..................................................................................... 5 Timing Characteristics .............................................................. 13 Timing Diagrams........................................................................ 13 Absolute Maximum Ratings.......................................................... 15 Thermal Resistance .................................................................... 15 ESD ...
Page 3
REVISION HISTORY 10/10—Rev Rev. C Changes to Force Output Voltage Parameter and Load Transient Response Parameter, Table 1............................................................5 Changes to Figure 52 ......................................................................29 Changes to Table 9 ..........................................................................32 9/09—Rev Rev. B Changes to Table 1, Measure ...
Page 4
AD5560 FUNCTIONAL BLOCK DIAGRAM 100kΩ 25kΩ 6kΩ Figure 1. Rev Page 07779-001 ...
Page 5
SPECIFICATIONS HCAV x ≤ ( V), HCAV x ≤ 2 5 gain (m), offset (c), and DAC offset registers are at default values; AGND = DGND = ...
Page 6
AD5560 Parameter Min Measure Current Ranges MEASURE CURRENT 1 Differential Input Voltage Range −0.64 −0.7 1 Output Voltage Span Offset Error −1 1 Offset Error Tempco Offset Error −1.5 1 Offset Error Tempco Offset Error −1.5 1 Offset Error Tempco ...
Page 7
Parameter Min MEASOUT Gain = 0.2 Linearity Error −5.5 −9 −4 Offset Error −30 1 Offset Error Tempco 1 NSD COMBINED LEAKAGE Leakage Current −37.5 −30 1 Leakage Current Tempco SENSE INPUT Leakage Current −2.5 1 Leakage Current Tempco 1 ...
Page 8
AD5560 Parameter Min SYS_FORCE Voltage Range Current Carrying Capability −25 Leakage Current −2.5 1 Leakage Current Tempco Path On Resistance 1 Pin Capacitance SYS_DUTGND Voltage Range AV SS Path On Resistance CURRENT CLAMP Clamp Accuracy Programmed clamp ...
Page 9
Parameter Min SETTLING TIME (FV, MEASURE CURRENT) Compensation Register 1 = 0x4880 (229 nF to 380 nF, ESR 74 to 140 mΩ (1200 mA EXTFORCE1 Range (900 mA EXTFORCE1 Range (500 mA EXTFORCE2 Range) ...
Page 10
AD5560 Parameter Min Comparator DAC Dynamic 1 Output Voltage Settling Time 1 Slew Rate 1 Digital-to-Analog Glitch Energy 1 Glitch Impulse Peak Amplitude REFERENCE INPUT VREF DC Input Impedance 1 VREF Input Current −10 1 VREF Range 2 COMPARATOR Error ...
Page 11
Parameter Min SPI INTERFACE LOGIC Logic Inputs Input High Voltage, V 1.7/2.0 IH Input Low Voltage Input Current −1 INH INL 1 Input Capacitance CMOS Logic Outputs Output High Voltage ...
Page 12
AD5560 Parameter Min 1 Power Supply Sensitivity ΔForced Voltage/ΔAV DD ΔForced Voltage/ΔAV SS ΔForced Voltage/ΔHCAV x DD ΔForced Voltage/ΔHCAV x SS ΔMeasured Current/ΔAV DD ΔMeasured Current/ΔAV SS ΔMeasured Current/ΔHCAV x DD ΔMeasured Current/ΔHCAV x SS ΔMeasured Voltage/ΔAV DD ΔMeasured Voltage/ΔAV ...
Page 13
TIMING CHARACTERISTICS HCAV x ≤ HCAV x ≥ maximum specifications, unless otherwise noted). Table 2. SPI Interface Parameter to 2 3.3 ...
Page 14
AD5560 SCLK SYNC t 5 DB23 SDI BUSY 1,3 LOAD FORCE EXTFORCE1 1 EXTFORCE2 2,3 LOAD FORCE EXTFORCE1 2,3 EXTFORCE2 RESET BUSY 1 LOAD ACTIVE DURING BUSY. 2 LOAD ACTIVE AFTER BUSY. 3 LOAD FUNCTION IS AVAILABLE ...
Page 15
ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Rating AGND −0 + AGND − +0 HCAV x to HCAV ...
Page 16
AD5560 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS CLALM KELALM TMPALM CPOH/CPO CPOL BUSY SDO DV CC DGND SCLK SDI SYNC RCLK RESET CLEN/LOAD HW_INH/LOAD NOTES CONNECT. 2. EXPOSED PAD ON TOP OF PACKAGE. EXPOSED PAD IS INTERNALLY ...
Page 17
Pin No. Mnemonic Description 18 VREF Reference Input for DAC Channels, Input Range 19, 44 AGND Analog Ground. 20, 30 Negative Analog Supply Voltage. These pins supply DACs and other high voltage circuitry, ...
Page 18
AD5560 TYPICAL PERFORMANCE CHARACTERISTICS 1.2 1.0 0.8 0.6 0.4 0.2 0 –0.2 0 10,000 20,000 30,000 40,000 CODE Figure 7. Force Voltage Linearity vs. Code, V 2.0 1.5 1.0 0.5 MEASOUT GAIN = 0.2 0 –0.5 –1.0 –1.5 MEASOUT GAIN ...
Page 19
HIGH 28V –5V, OFFSET DAC = 0xD1D DD LOW 5V –25V OFFSET DAC = 0xD4EB DD NOM: AV /AV = ±16.25V, OFFSET DAC = 0x8000 0.0375 ...
Page 20
AD5560 0.15 EXTFORCE1A EXTFORCE2B EXTFORCE1B 0.10 EXTMEASIH1 SENSE EXTFORCE1C 0.05 EXTMEASIH2 SYS_FORCE EXTFORCE2A 0 EXTMEASIL SYS_SENSE –0.05 –0.10 –0.15 –0.20 – STRESS VOLTAGE (V) Figure 19. Leakage Current vs. Stress Voltage 0 STRESS 0.7 0.6 ...
Page 21
NOMINAL –0.004 –0.005 HIGH –0.006 –0.007 TEMPERATURE (°C) Figure 25. MV Gain Error vs. Temperature, MEASOUT Gain = 1 1.0 0.9 HIGH 0.8 NOMINAL 0.7 LOW 0.6 0.5 0.4 0.3 0.2 ...
Page 22
AD5560 FORCE 1 SYNC 3 CH1 50mV B M200µ 10.4% CH3 Figure 31. Range Change EXTFORCE2, Safe Mode μF Load LOAD FORCE 1 SYNC 3 CH1 50mV ...
Page 23
TRIGGER 2 FORCE 1 B CH1 100mV CH2 5V M40µ 120.4µs Figure 37. Safe Mode 10% to 90%, EXTFORCE2 Range, 10 μF Load 2 +16. –16.5V SS 1.9 1.8 1.7 1.6 1.5 1.4 ...
Page 24
AD5560 MEASOUT – 25° +16.25V –16.25V REF OFFSET DAC = 0x8000 EXTFORCE1/1.2A RANGE LOAD 0 TO 3.7V STEP C = 10µF CERAMIC 2 ...
Page 25
MI: GAIN 0 –40 –60 –80 –100 DV = +5.25V +16.5V –16. –120 10 100 1k 10k 100k FREQUENCY (Hz) Figure 49. ACPSRR of DV vs. Frequency CC 0 MI: GAIN ...
Page 26
AD5560 TERMINOLOGY Offset Error Offset error is a measure of the difference between the actual voltage and the ideal voltage at midscale or at zero current expressed in millivolts (mV) or percentage of full-scale range (%FSR). Gain Error Gain error ...
Page 27
THEORY OF OPERATION The AD5560 is a single-channel, device power supply for use in semiconductor automatic test equipment. All the DAC levels required to operate the device are available on chip. This device contains programmable modes to force a pin ...
Page 28
... AD5560 devices. When selected, the anode of these diodes is connected to GPO and the cathode to AGND. The AD5560 evaluation board uses the ON Semiconductor® ADT7461 temperature sensor for the purpose of analyzing the temperature at different points across the die. ...
Page 29
The AD5560 has three compensation modes: safe mode, autocompensation mode, and manual compensation mode, all of which are described in more Stability section. The range of suggested compensation capacitors allows ...
Page 30
AD5560 Master in FV Mode, Slaves in Force Current (FI) Mode The master device is placed into FV mode, and all slave devices into force current (FI) mode. The measured current of the master device (MASTER_OUT) is applied to the ...
Page 31
... The third set of temperature sensors is an array of thermal diodes scattered across the die. These diodes allow the user to evaluate the temperature of different parts of the die and are of great use to determine the temperature gradients across the die and the temperature of the accurate portions of the die when the device is dissipating high power ...
Page 32
AD5560 V is another inportant voltage level that is used in other MIN parts of the circuit. When using a MEASOUT gain of 0.2, the V level is used to scale the voltage range; therefore, when MIN choosing supply rails, ...
Page 33
VREF VTOP LOW VOLTAGE OFFSET DAC VBOT REFGND R 10R INTERNAL MEASI LOW I AMP SENSE INTERNAL MEASI HIGH R 10R DUTGND SENSE NOTES 1. att: ATTENUATION FOR EXTERNAL MEASOUT × 0.20 FOR OUTPUT VOLTAGE RANGE 0V TO 5.125V (WITH ...
Page 34
AD5560 FORCE AMPLIFIER STABILITY There are three modes for configuring the force amplifier: safe mode, autocompensation mode, and manual compensation mode. Manual compensation mode has highest priority, followed by safe mode, then autocompensation mode. Safe Mode Selected through Compensation Register ...
Page 35
POLES AND ZEROS IN A TYPICAL SYSTEM Typical closed loop systems have one dominant pole in the feedback path, providing −20 dB/decade gain roll off and 90° of phase shift so that the gain decreases where there ...
Page 36
AD5560 stability problems. This is most likely to be the case when there are both a large C and large The R resistor is intended to solve this problem. Again prudent not to ...
Page 37
Calculate F , the ESR zero frequency, using F Z 1/(2πRcCr). 11 > Fug, the load pole is above the bandwidth of the P AD5560. Ignore it with Z[2:0] algorithm 12 ...
Page 38
AD5560 The transfer function for these 16-bit DACs is ⎛ DAC CODE = × × ⎜ ⎜ VCLH , VCLL . 5 125 V REF 16 ⎝ 2 ⎛ ⎞ OFFSET _ DAC _ CODE + ⎜ ⎟ DUTGND ⎝ ...
Page 39
REFERENCE SELECTION The voltage applied to the VREF pin determines the output voltage range and span applied to the force amplifier, clamp, and comparator inputs and the current ranges. This device can be used with a reference input ranging from ...
Page 40
AD5560 PACKAGE COMPOSITION AND MAXIMUM VERTICAL FORCE The exposed pad and leads of the TQFP package have a 100% tin finish. The exposed paddle is connected internally to AV The simulated maximum allowable force for a single lead is 0.18 ...
Page 41
NEW RAMP YES CHANGE SELECT RAMP SIZE STEP SIZE? NO CHANGE YES CLOCK DIVISION? NO YES CHANGE RAMP START? NO WRITE RAMP END CODE RAMP MODE ENABLE RAMP YES UPDATE DAC CODE? NO YES INTERRUPT RAMP? ALARM RAMP ...
Page 42
AD5560 SERIAL INTERFACE The AD5560 contains an SPI-compatible interface operating at clock frequencies MHz. To minimize both the power consumption of the device and on-chip digital noise, the interface powers up fully only when the device ...
Page 43
If Bits[8:7] of the system control register (Address 0x1) are high, then the CLEN and HW_INH operate as normal, and the update waits until BUSY goes high (this way multiple channels can still be synchronized by simply tying BUSY pins ...
Page 44
AD5560 CONTROL REGISTERS DPS AND DAC ADDRESSING The serial word assignment consists of 24 bits, as shown in Table 16. All write-to registers can be read back. There are some read-only registers (Address 0x43 and Address 0x44). DAC x2 registers ...
Page 45
Table 18. DPS Register 1 Address Default 0x2 0x0000 Bit Name Function 15 SW-INH This bit enables the force amplifier when high and disables the amplifier when low. This bit is AND’d with the HW_INH hardware inhibit pin. 14 Reserved ...
Page 46
AD5560 Table 19. DPS Register 2 Address Default 0x3 0x0000 Bit Name 15 SF0 14 SR[2: GPO 10 SLAVE, GANGIMODE 9 8 INT10K 7 Guard high-Z 6:0 Unused Data Bits, MSB First Function System force and sense ...
Page 47
The AD5560 has three compensation modes. The power-on default mode is into any load. Use Compensation Register 1 to configure the device for autocompensation, where the user inputs the CDUT and ESR bits, and the AD5560 chooses the most appropriate ...
Page 48
AD5560 Table 21. Compensation Register 2 Address Default 0x5 0x0110 Bit Name 15 Manual compensation 14 R Z[2: P[2: m[1: F[2: ...
Page 49
Register 0x6 allows the user to enable or disable any of the alarm flags that are not required. If disabled, that particular alarm no longer flags on the appropriate open-drain pin; however, the alarm status is still available in both ...
Page 50
AD5560 Table 23. Diagnostic Register Address Default 0x7 0x0000 Bit Name 15 DIAG select[3: TSENSE select[3: Data Bits, MSB First Function DIAG select selects the set of diagnostic signals that can be ...
Page 51
Address Default 0x7 0x0000 Bit Name 6 Test Force AMP[1:0] 5 4:0 Reserved Data Bits, MSB First Function Force amplifier 24 NPNs These register bits allow disabling of stages of the force amplifier. ...
Page 52
AD5560 Table 24. Other Registers Address Register 0x8 FIN DAC x1 0x9 FIN DAC m 0xA FIN DAC c 0xB Offset DAC x 0xC OSD DAC x 0xD CLL DAC x1 0xE CLL DAC m 0xF CLL DAC c 0x10 ...
Page 53
Address Register 0x3C CPH DAC c EXT Range 1 0x3D DGS DAC 0x3E Ramp end code 0x3F Ramp step size 0x40 RCLK divider 0x41 Enable ramp 0x42 Interrupt ramp Default Data Bits, MSB First 0x8000 D15 to D0. 0x3333 D15 ...
Page 54
AD5560 Table 25. Alarm Status and Clear Alarm Status Register Address Register Default 0x43 Alarm status 0x0000 0x44 Alarm status 0x0000 and clear alarm 0x45 CPL DAC x1 0x0000 0x46 CPL DAC m 0xFFFF 0x47 CPL DAC c 0x8000 0x48 ...
Page 55
READBACK MODE The AD5560 allows data readback via the serial interface from every register directly accessible to the serial interface, which is all registers except the DAC register (x2 calibrated register). To read back contents of a register ...
Page 56
AD5560 Table 26. AD5560 Truth Table of Switches Reg Bit Name Bit SW1 System Gain0, X Control Gain1 Register FINGND CPO DPS Register SW-INH 5 ...
Page 57
USING THE HCAV x AND HCAV DD The first set of power supplies, AV and the DAC levels and associated circuitry. They also supply the force amplifier stage for the low current ranges (ranges using internal sense ...
Page 58
AD5560 REQUIRED EXTERNAL COMPONENTS The minimum required external components are shown in the block diagram in Figure 58. Decoupling is very dependent on the type of supplies used, the board layout, and the noise in the system possible ...
Page 59
POWER SUPPLY DECOUPLING In any circuit where accuracy is important, careful consid- eration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5560 is mounted should be designed ...
Page 60
... ROTATED 90 ° CCW ORDERING GUIDE Model 1 Temperature Range AD5560JSVUZ T = 25°C to +90 J AD5560JSVUZ-REEL T = 25°C to +90 J EVAL-AD5560EBUZ RoHS Compliant Part junction temperature. J ©2008-2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07779-0-10/10(C) 0.675 1.20 0.872 5 ...