EVAL-AD5560EBUZ Analog Devices Inc, EVAL-AD5560EBUZ Datasheet - Page 53
EVAL-AD5560EBUZ
Manufacturer Part Number
EVAL-AD5560EBUZ
Description
Evaluation Board
Manufacturer
Analog Devices Inc
Datasheet
1.AD5560JSVUZ-REEL.pdf
(60 pages)
Specifications of EVAL-AD5560EBUZ
Main Purpose
Power Management, Power Supply Supervisor/Tracker/Sequencer
Utilized Ic / Part
AD5560
Primary Attributes
*
Secondary Attributes
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Embedded
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Address
0x3C
0x3D
0x3E
0x3F
0x40
0x41
0x42
CPH DAC c EXT Range 1
DGS DAC
Ramp end code
Ramp step size
RCLK divider
Enable ramp
Interrupt ramp
Register
Default
0x8000
0x3333
0x0000
0x0001
0x0001
0x0000
0x0000
Data Bits, MSB First
D15 to D0.
D15 to D0 DUTGND SENSE DAC, 0 V to 5 V range.
D15 to D0; this is the ramp end code. The ramp start code is the code that is in the FIN
DAC register.
0000 0000 D6 to D0.
D6:D0 set the ramp step size in increments of 16 LSB per code, with a 5 V reference,
16 LSB = 6.1 mV.
For example,
000 0000 = 16 LSBs (6.1 mV) step
000 0001 = 16 LSBs (6.1 mV) step
…
111 1111 = 2032 LSBs (775 mV) step.
0000 0000 D7 to D0.
D7:D0 set the RCLK divider.
0000 0000 = ÷ 1
0000 0001 = ÷ 1
0000 0010 = ÷ 2
0000 0011 = ÷ 3
…
1111 1111 = ÷ 255
0xFFFF to enable.
0x0000 to interrupt.
Rev. C | Page 53 of 60
AD5560
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