EVAL-ADF7021-VDB2Z Analog Devices Inc, EVAL-ADF7021-VDB2Z Datasheet
EVAL-ADF7021-VDB2Z
Specifications of EVAL-ADF7021-VDB2Z
Related parts for EVAL-ADF7021-VDB2Z
EVAL-ADF7021-VDB2Z Summary of contents
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FEATURES High performance, low power, narrow-band transceiver Enhanced performance ADF7021-N with external VCO Frequency bands using external VCO: 80 MHz to 960 MHz Improved adjacent channel power (ACP) and adjacent channel rejection (ACR) compared with the ADF7021-N Programmable IF filter ...
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ADF7021-V TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 General Description ......................................................................... 3 Specifications ..................................................................................... 4 RF and PLL Specifications ........................................................... 4 Transmission Specifications ........................................................ 5 Receiver Specifications ................................................................ 6 ...
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GENERAL DESCRIPTION The ADF7021 high performance, low power, narrow-band RF transceiver based on the ADF7021-N. The architecture of the ADF7021-V transceiver is similar to that of the ADF7021-N except that an external VCO is used by the on-chip ...
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... SPECIFICATIONS 3.6 V, GND = measurements are performed with the EVAL-ADF7021-VDBxZ using the PN9 data sequence, unless otherwise noted. The version number of ETSI EN 300 200-1 is V2.3.1. LBW = loop bandwidth and IFBW = IF filter bandwidth. RF AND PLL SPECIFICATIONS Table 1. Parameter RF CHARACTERISTICS Phase Frequency Detector (PFD) ...
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TRANSMISSION SPECIFICATIONS LBW = loop bandwidth. Table 2. Parameter DATA RATE 2FSK 3FSK 4FSK MODULATION Frequency Deviation (f ) DEV Frequency Deviation Resolution Gaussian Filter Bandwidth Time (BT) Raised Cosine Filter Alpha TRANSMIT POWER Maximum Transmit Power 1 Transmit Power ...
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... RF 1 Measured as maximum unmodulated power. 2 Suitable for ETSI 500 mW Tx requirements. 3 Conductive filtered harmonic emissions measured on the EVAL-ADF7021-VDBxZ, which includes a T-stage harmonic filter (two inductors and one capacitor). RECEIVER SPECIFICATIONS LBW = loop bandwidth and IFBW = IF filter bandwidth. Table 3. Parameter Min DATA RATE 2FSK 0 ...
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Parameter Min Raised Cosine 2FSK Sensitivity at 0.25 kbps Sensitivity at 1 kbps Sensitivity at 2.4 kbps Sensitivity at 4.8 kbps Sensitivity at 9.6 kbps 3FSK Sensitivity at 4.8 kbps Raised Cosine 3FSK Sensitivity at 4.8 kbps 4FSK Sensitivity at ...
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... For received signal levels < −100 dBm recommended that the RSSI readback value be averaged over a number of samples to improve RSSI accuracy at low input power. 5 Filtered conductive receive spurious emissions are measured on the EVAL-ADF7021-VDBxZ, which includes a T-stage harmonic filter (two inductors and one capacitor). Typ ...
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DIGITAL SPECIFICATIONS Table 4. Parameter Min TIMING INFORMATION Chip Enabled to Regulator Ready Chip Enabled to Tx Mode TCXO Reference XTAL Chip Enabled to Rx Mode TCXO Reference XTAL Tx-to-Rx Turnaround Time LOGIC INPUTS Input High Voltage, V 0.7 × ...
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... POWER-DOWN CURRENT CONSUMPTION Low Power Sleep Mode 1 The transmit current consumption tests used the same combined PA and LNA matching network as that used on the EVAL-ADF7021-VDBxZ evaluation boards. Improved PA efficiency is achieved by using a separate PA matching network. 2 Device current only. VCO and TCXO currents are excluded. ...
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TIMING DIAGRAMS Serial Interface SCLK t 1 SDATA DB31 (MSB) SLE SCLK SDATA REG 7 DB0 (CONTROL BIT C1) SLE t 3 SREAD t 8 2FSK/3FSK Timing ±1 × DATA RATE/32 TxRxCLK TxRxDATA TxRxCLK TxRxDATA FETCH ...
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ADF7021-V 4FSK Timing In 4FSK receive mode, MSB/LSB synchronization should be guaranteed by detection of the SWD pin in the receive bit stream. t SYMBOL t BIT SLE TxRxCLK Rx SYMBOL TxRxDATA MSB Tx/Rx MODE SLE TxRxCLK Tx SYMBOL TxRxDATA ...
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UART/SPI Mode UART mode is enabled by setting Register 0, Bit DB28 to 1. SPI mode is enabled by setting Register 0, Bit DB28 to 1 and setting Register 15, Bits[DB19:DB17] to 0x7. The transmit/receive data clock is available on ...
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ADF7021-V ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 7. Parameter Rating GND −0 Analog I/O Voltage to GND −0 VDDx + 0 Digital ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 8. Pin Function Descriptions Pin No. Mnemonic Description 1 VCOIN Do not connect. 2 CREG1 Regulator Voltage for PA Block. Place a series 3.9 Ω resistor and a 100 nF capacitor between this pin ...
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ADF7021-V Pin No. Mnemonic Description 27 SREAD Serial Data Output. This pin is used to feed readback data from the ADF7021-V to the microcontroller. The SCLK input is used to clock each readback bit (for example, AFC or ADC) from ...
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TYPICAL PERFORMANCE CHARACTERISTICS –80 –90 –100 –110 –120 –130 –140 –150 –160 1 10 100 1k FREQUENCY OFFSET (kHz) Figure 11. Phase Noise Response at 460 MHz, V –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 1 ...
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ADF7021 –10 –20 –30 –40 –50 RC2FSK –60 –70 –80 867.97 867.98 867.99 868.00 868.01 FREQUENCY (MHz) Figure 17. Output Spectrum in 2FSK and Raised Cosine 2FSK Modes 10 DATA RATE = 9.6kbps DATA = PRBS9 0 f ...
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DATA RATE = 1.2kbps f RF FREQ = 868MHz 0.5 IFBW = 9kHz 0.4 0.3 0.2 0.1 0 –130 –125 –120 –115 RF INPUT POWER (dBm) Figure 23. 2FSK Sensitivity vs. V and Temperature at 868 MHz DD 0.6 ...
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ADF7021-V –100 –102 –104 –106 –108 DISCRIMINATOR BANDWIDTH = –110 2× FSK FREQUENCY DEVIATION –112 –114 –116 DISCRIMINATOR BANDWIDTH = 1× FSK FREQUENCY DEVIATION –118 0 0.2 0.4 0.6 MODULATION INDEX Figure 29. 2FSK Sensitivity vs. Modulation Index and Correlator ...
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... This provides a good compromise between in-band phase noise and out-of-band spurious rejection. Widening the LBW excessively reduces the time spent jumping between frequencies, but it can cause insufficient spurious attenuation. The loop filter design on the EVAL-ADF7021-VDBxZ should be used for optimum performance. Rev Page ADF7021-V ...
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ADF7021-V The free design tool ADIsimSRD™ Design Studio can also be used to design loop filters for the ADF7021-V. See the ADIsimSRD Design Studio website (www.analog.com/adisimsrd) for details). N Counter The feedback divider in the ADF7021-V PLL consists of an ...
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VOLTAGE CONTROLLED OSCILLATOR (VCO) To minimize feedthrough and spurious emissions, the external VCO must be chosen to operate at a minimum of twice the required RF frequency. The VCO frequency is divided by 2 inside the synthesizer loop, providing the ...
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ADF7021-V TRANSMITTER RF OUTPUT STAGE The power amplifier (PA) of the ADF7021-V is based on a single-ended, controlled current, open-drain amplifier that has been designed to deliver dBm into a 50 Ω load at a maximum frequency ...
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Setting the Transmit Data Rate In all modulation modes except for oversampled 2FSK mode, an accurate clock is provided on the TxRxCLK pin to latch the data from the microcontroller into the transmit section at the required data rate. The ...
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ADF7021-V The signal mapping of the input binary transmit data to the three-level convolutional output is shown in Table 9. The convolutional encoder restricts the maximum number of sequential +1s or −1s to two and delivers an equal number of ...
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MODULATION AND FILTERING OPTIONS The various modulation and data filtering options for the ADF7021-V are described in Table 10. Table 10. Modulation and Filtering Options Modulation Data Filtering Binary FSK 2FSK None 1 MSK None OQPSK with Half Sine None ...
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ADF7021-V RECEIVER SECTION RF FRONT END The ADF7021-V is based on a fully integrated, low IF receiver architecture. The low IF architecture facilitates a very low external component count and does not suffer from powerline-induced interference problems. Figure 44 shows ...
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Offset Correction Clock In Register 3, the user should set the BBOS_CLK_DIVIDE bits (Bits[DB5:DB4]) to give a baseband offset clock (BBOS CLK) frequency between 1 MHz and 2 MHz. BBOS CLK (Hz) = XTAL/(BBOS_CLK_DIVIDE) where BBOS_CLK_DIVIDE can be set to ...
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ADF7021-V DEMODULATION, DETECTION, AND CDR System Overview An overview of the demodulation, detection, and clock and data recovery (CDR) of the received signal on the ADF7021-V is shown in Figure 46. LIMITERS I CORRELATOR Q DEMODULATOR MUX LINEAR DEMODULATOR TxRxDATA ...
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Bit Slicer/Threshold Detection 2FSK demodulation can be implemented using the correlator FSK demodulator or the linear FSK demodulator. In both cases, threshold detection is used for data recovery at the output of the postdemodulator filter. The output signal levels ...
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ADF7021-V RECEIVER SETUP Correlator Demodulator Setup To enable the correlator for various modulation modes, see Table 15. Table 15. Enabling the Correlator Demodulator DEMOD_SCHEME Received Modulation (Register 4, Bits[DB6:DB4]) 2FSK 001 3FSK 010 4FSK 011 To optimize receiver sensitivity, the ...
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CDR Setup In 3FSK, a transmit preamble of at least 40 bits of continuous 1s is recommended to ensure a maximum number of symbol transitions for the CDR to acquire lock. The clock and data recovery for 3FSK requires ...
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ADF7021-V Correlator Demodulator and Low Modulation Indexes The modulation index in 2FSK is defined as × DEV Modulation Index Data Rate The receiver sensitivity performance and receiver frequency tolerance can be maximized at low modulation indexes by ...
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AUTOMATIC SYNC WORD DETECTION (SWD) The ADF7021-V also supports automatic detection of the sync or ID fields. To activate this mode, the sync (or ID) word must be preprogrammed into the ADF7021-V. In receive mode, this preprogrammed word is compared ...
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ADF7021-V APPLICATIONS INFORMATION IF FILTER BANDWIDTH CALIBRATION The IF filter should be calibrated on every power-up in receive mode to correct for errors in the bandwidth and filter center frequency due to process variations. The automatic calibration requires no external ...
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... Figure 49 shows the ADF7021 configuration where the internal Tx/Rx switch is used with a combined LNA/PA matching network. This is the configuration used on the EVAL-ADF7021-VDBxZ evaluation board. For most applica- tions, the slight performance degradation caused by the internal Tx/Rx switch is acceptable, allowing the user to take advantage of the cost-saving potential of this solution ...
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ADF7021-V External Tx/Rx Switch Figure 50 shows a configuration using an external Tx/Rx switch. This configuration allows independent optimization of the matching and filter network in the transmit and receive paths. Therefore more flexible and less difficult to ...
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RFIN LNA RFIN INTERNAL SOURCE Figure 51. Image Rejection Calibration Using the Internal Calibration Source and a Microcontroller The calibration results are valid over changes in the ADF7021-V supply voltage. However, there is some variation with temperature. A typical plot ...
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ADF7021-V The recommended programming sequences for transmit and receive are shown in Figure 54 and Figure 55, respectively. REFERENCE CE HIGH WAIT 50µs (REGULATOR POWER-UP) CHECK FOR REGULATOR READY OPTIONAL. ONLY NECESSARY IF PA RAMP-DOWN IS REQUIRED. The difference in ...
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TCXO REFERENCE TURN ON EXTERNAL VCO AND ALLOW ADEQUATE SETTLING CE HIGH WAIT 50µs (REGULATOR POWER-UP) CHECK FOR REGULATOR READY WRITE TO REGISTER 3 WRITE TO REGISTER 6 (SETS UP IF FILTER FINE CALIBRATION) WRITE TO REGISTER 5 (STARTS IF ...
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... Figure 56. Typical Application Circuit (Regulator Capacitors and Power Supply Decoupling Not Shown) For recommended component values, see the ADF7021-V evaluation board data sheet and the AN-859 Application Note, accessible from the ADF7021-V product page. Follow the refer- ence design schematic closely to ensure optimum performance in narrow-band applications ...
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SERIAL INTERFACE The serial interface allows the user to program the 16 32-bit registers using a 3-wire interface (SCLK, SDATA, and SLE). It consists of a level shifter, 32-bit shift register, and 16 latches. Signals should be CMOS compatible. The ...
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ADF7021-V Silicon Revision Readback The silicon revision readback word is valid without setting any other registers. The silicon revision word is coded with four quartets in BCD format. The product code (PC) is coded with three quartets extending from Bit ...
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REGISTER 0—N REGISTER MUXOUT INTEGER_N TR1 Tx/Rx 0 TRANSMIT 1 RECEIVE U1 UART_MODE 0 DISABLED 1 ENABLED MUXOUT REGULATOR_READY (DEFAULT FILTER_CAL_COMPLETE DIGITAL_LOCK_DETECT RSSI_READY 1 0 ...
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ADF7021-V REGISTER 1—OSCILLATOR REGISTER RESERVED RFD1 RF_DIVIDE_BY_2 0 1 VE1 0 1 • The R_COUNTER and XTAL_DOUBLER relationship is as follows: If XTAL_DOUBLER = 0, XTAL = PFD R _ COUNTER If XTAL_DOUBLER = 1, × XTAL 2 = PFD ...
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REGISTER 2—TRANSMIT MODULATION REGISTER TxDATA_ INVERT Tx_FREQUENCY_DEVIATION DI2 DI1 TxDATA_INVERT 0 0 NORMAL 0 1 INVERT CLK 1 0 INVERT DATA 1 1 INV CLK AND DATA TFD9 ... TFD3 TFD2 0 ... ... ...
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ADF7021-V REGISTER 3—TRANSMIT/RECEIVE CLOCK REGISTER AGC_CLK_DIVIDE SEQ_CLK_DIVIDE GD6 GD5 GD4 GD3 GD2 GD1 ... ... ... ... ... ... • Baseband offset ...
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REGISTER 4—DEMODULATOR SETUP REGISTER POST_DEMOD_BW IF_FILTER _ IFB2 IFB1 9kHz 0 1 13.5kHz 1 0 18.5kHz 1 1 INVALID DW10 . DW6 DW5 DW4 DW3 DW2 DW1 POST_DEMOD_BW ...
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ADF7021-V REGISTER 5—IF FILTER SETUP REGISTER IR_GAIN_ ADJUST_MAG PM4 PD1 IR_PHASE_ADJUST_DIRECTION 0 ADJUST ADJUST Q CH GM5 GM4 GM3 GM2 GM1 ...
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REGISTER 6—IF FINE CALIBRATION SETUP REGISTER IF_CAL_DWELL_TIME IRD1 IR_CAL_SOURCE ÷2 0 SOURCE ÷2 OFF 1 SOURCE ÷2 ON IR_CAL_SOURCE_ IRC2 IRC1 DRIVE_LEVEL 0 0 OFF 0 1 LOW 1 0 MED 1 1 HIGH CD7 ... CD3 0 0 ... ...
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ADF7021-V REGISTER 7—READBACK SETUP REGISTER RB3 READBACK_SELECT 0 DISABLED 1 ENABLED • Readback of the measured RSSI value is valid only in Rx mode. Readback of the battery voltage, temperature sensor, or voltage at the external ADCIN pin is not ...
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REGISTER 8—POWER-DOWN TEST REGISTER Rx_RESET DB15 DB14 CR1 RR2 CR1 COUNTER_RESET 0 NORMAL 1 RESET RR2 CDR_RESET 0 NORMAL 1 RESET RR1 DEMOD_RESET 0 NORMAL 1 RESET PD7 PA_ENABLE_Rx_MODE 0 PA OFF SW1 Tx/Rx_SWITCH_ENABLE 0 DEFAULT (ON) ...
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ADF7021-V REGISTER 9—AGC REGISTER LNA_ BIAS ML1 MIXER_LINEARITY 0 DEFAULT 1 HIGH LI2 LI1 LNA_BIAS 0 0 800µA (DEFAULT) LM1 LNA_MODE 0 DEFAULT 1 REDUCED GAIN FI1 FILTER_CURRENT 0 LOW 1 HIGH FG2 FG1 FILTER_GAIN ...
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REGISTER 10—AFC REGISTER MAX_AFC_RANGE KP3 KP2 KP1 MAX_AFC_RANGE ... MA3 MA2 MA1 MA8 0 ... ... ... 0 ...
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ADF7021-V REGISTER 11—SYNC WORD DETECT REGISTER REGISTER 12—SWD/THRESHOLD SETUP REGISTER ILx SWD_MODE Lock threshold locks the threshold of the envelope detector. This has the effect of locking the slicer in linear demodulation SYNC_BYTE_SEQUENCE Figure 73. Register ...
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REGISTER 13—3FSK/4FSK DEMODULATION REGISTER See the Receiver Setup section for information about programming these settings. 3FSK_PREAMBLE_ TIME_VALIDATE 3FSK_CDR_THRESHOLD VT3 VT7 ... 0 0 ... 0 0 ... 0 0 ... 0 ... 0 . ... . . ... . 1 ...
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ADF7021-V REGISTER 14—TEST DAC REGISTER TEST_DAC_GAIN EFx ED_LEAK_FACTOR ERx PULSE_EXTENSION LEAKAGE = 0 0 2^– 2^– 2^– 2^–11 4 2^–12 5 2^–13 6 2^–14 7 2^–15 PEx ED_PEAK_RESPONSE 0 FULL RESPONSE TO PEAK 1 ...
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REGISTER 15—TEST MODE REGISTER ANALOG_TEST_ MODES COx CAL_OVERRIDE 0 AUTO CAL 1 OVERRIDE GAIN 2 OVERRIDE BW 3 OVERRIDE BW AND GAIN RD1 REG1_PD 0 NORMAL 1 POWER-DOWN FH1 FORCE_LD_HIGH 0 NORMAL 1 FORCE AMx ANALOG_TEST_MODES 0 BAND GAP VOLTAGE ...
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... Model Temperature Range ADF7021-VBCPZ −40°C to +85°C ADF7021-VBCPZ-RL −40°C to +85°C EVAL-ADF70XXMBZ2 EVAL-ADF7021-VDB1Z EVAL-ADF7021-VDB2Z RoHS Compliant Part. ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 0.60 MAX 0.60 MAX ...