FDC6312P Fairchild Semiconductor, FDC6312P Datasheet - Page 2

• Manufacturer Part Number: FDC6312P
• Description: MOSFET P-CH DUAL 20V SSOT-6
• Manufacturer: Fairchild Semiconductor
• Series: PowerTrench®r

Specifications of FDC6312P

• Fet Type: 2 P-Channel (Dual)
• Fet Feature: Logic Level Gate
• Rds On (max) @ Id, Vgs: 115 mOhm @ 2.3A, 4.5V
• Drain To Source Voltage (vdss): 20V
• Current - Continuous Drain (id) @ 25° C: 2.3A
• Vgs(th) (max) @ Id: 1.5V @ 250µA
• Gate Charge (qg) @ Vgs: 7nC @ 4.5V
• Input Capacitance (ciss) @ Vds: 467pF @ 10V
• Power - Max: 700mW
• Mounting Type: Surface Mount
• Package / Case: 6-SSOT, SuperSOT-6
• Configuration: Dual
• Transistor Polarity: P-Channel
• Resistance Drain-source Rds (on): 0.115 Ohm @ 4.5 V
• Forward Transconductance Gfs (max / Min): 5.3 S
• Drain-source Breakdown Voltage: 20 V
• Gate-source Breakdown Voltage: +/- 8 V
• Continuous Drain Current: 2.3 A
• Power Dissipation: 960 mW
• Maximum Operating Temperature: + 150 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 55 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: FDC6312P; FDC6312PTR

Notes:
1. R
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300 s, Duty Cycle < 2.0%
Electrical Characteristics
Symbol
Off Characteristics
BV
I
I
I
On Characteristics
V
R
I
g
Dynamic Characteristics
C
C
C
Switching Characteristics
t
t
t
t
Q
Q
Q
Drain–Source Diode Characteristics and Maximum Ratings
I
V
the drain pins. R
f
DSS
GSSF
GSSR
D(on)
d(on)
r
d(off)
S
BV
V
FS
GS(th)
SD
DS(on)
iss
oss
rss
g
gs
gd
JA
GS(th)
DSS
T
T
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
DSS
J
J
Drain–Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate–Body Leakage, Forward
Gate–Body Leakage, Reverse
Gate Threshold Voltage
Gate Threshold Voltage
Temperature Coefficient
Static Drain–Source
On–Resistance
On–State Drain Current
Forward Transconductance
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn–On Delay Time
Turn–On Rise Time
Turn–Off Delay Time
Turn–Off Fall Time
Total Gate Charge
Gate–Source Charge
Gate–Drain Charge
Maximum Continuous Drain–Source Diode Forward Current
Drain–Source Diode Forward
Voltage
JC
is guaranteed by design while R
a) 130 C/W when
mounted on a 0.125
in
copper.
2
Parameter
pad of 2 oz.
(Note 2)
(Note 2)
CA
is determined by the user's board design.
V
I
V
V
V
V
I
V
V
V
V
V
V
V
f = 1.0 MHz
V
V
V
V
V
T
D
D
A
GS
DS
GS
GS
DS
GS
GS
GS
GS
GS
DS
DS
DD
GS
DS
GS
GS
b) 140°/W when mounted
= –250 A,Referenced to 25 C
= –250 A,Referenced to 25 C
= 25°C unless otherwise noted
=–4.5 V, I
= –16 V,
= V
= –5 V,
= –10 V,
= –10 V,
= 0 V, I
= 8 V,
= –8 V,
= –4.5 V,
= –2.5 V,
= –1.8 V,
= –4.5 V,
= –10 V,
= –4.5 V,
= –4.5 V
= 0 V,
on a .004 in
copper
Test Conditions
GS
, I
D
D
I
= –250 A
= –250 A
D
2
S
pad of 2 oz
=–2.3A, T
= –0.8 A
V
V
V
I
I
I
V
I
GS
DS
D
D
D
V
I
I
R
D
DS
D
D
GS
DS
= –2.3 A
= –1.9 A
= –1.6 A
GEN
= –2.3 A,
= 0 V
= 0 V
= –3.5 A
= –1 A,
= 0 V
= 0 V,
= –5 V
= 6
J
=125 C
(Note 2)
–20
Min
–0.4
–7
c) 180°/W when mounted on a
minimum pad.
Typ Max Units
–0.9
–0.7
–11
116
166
112
467
5.3
4.4
1.0
0.8
92
85
38
13
18
2
8
8
–100
–1.5
–0.8
–1.2
100
115
155
225
150
–1
16
23
32
16
7
FDC6312P Rev C (W)
mV/ C
mV/ C
m
nC
nC
nC
nA
nA
pF
pF
pF
ns
ns
ns
ns
V
V
A
S
A
V
A