FDG6318PZ Fairchild Semiconductor, FDG6318PZ Datasheet - Page 6

• Manufacturer Part Number: FDG6318PZ
• Description: MOSFET P-CH DUAL 20V SC70-6
• Manufacturer: Fairchild Semiconductor

Specifications of FDG6318PZ

• Fet Type: 2 P-Channel (Dual)
• Fet Feature: Logic Level Gate
• Rds On (max) @ Id, Vgs: 780 mOhm @ 500mA, 4.5V
• Drain To Source Voltage (vdss): 20V
• Current - Continuous Drain (id) @ 25° C: 500mA
• Vgs(th) (max) @ Id: 1.5V @ 250µA
• Gate Charge (qg) @ Vgs: 1.62nC @ 4.5V
• Input Capacitance (ciss) @ Vds: 85.4pF @ 10V
• Power - Max: 300mW
• Mounting Type: Surface Mount
• Package / Case: SC-70-6, SC-88, SOT-363
• Configuration: Dual
• Transistor Polarity: P-Channel
• Resistance Drain-source Rds (on): 0.78 Ohm @ 4.5 V
• Forward Transconductance Gfs (max / Min): 1.1 S
• Drain-source Breakdown Voltage: 20 V
• Gate-source Breakdown Voltage: +/- 12 V
• Continuous Drain Current: 0.5 A
• Power Dissipation: 300 mW
• Maximum Operating Temperature: + 150 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 55 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

©2003 Fairchild Semiconductor Corporation
PSPICE Electrical Model
.SUBCKT FDG6318PZ 2 1 3 ;
CA 12 8 0.6e-10
CB 15 14 1.1e-10
CIN 6 8 0.75e-10
DBODY 5 7 DBODYMOD
DBREAK 7 11 DBREAKMOD
DPLCAP 10 6 DPLCAPMOD
EBREAK 5 11 17 18 -23.3
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 5 10 8 6 1
EVTHRES 6 21 19 8 1
EVTEMP 6 20 18 22 1
IT 8 17 1
LDRAIN 2 5 1e-9
LGATE 1 9 0.47e-9
LSOURCE 3 7 0.47e-9
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 280e-3
RGATE 9 20 12.4
RLDRAIN 2 5 10
RLGATE 1 9 4.7
RLSOURCE 3 7 4.7
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 190e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*20),2.5))}
.MODEL DBODYMOD D (IS = 7.7e-11 N=1.277 RS = 1e-3 TRS1 = 2.8e-1 TRS2 = 3e-4 XTI=0 IKF=0.5 CJO = 3.9e-11
TT=33e-9 M = 0.50)
.MODEL DBREAKMOD D (RS = 5.3e-1 TRS1 = 5.5e-3 TRS2 = -9e-5)
.MODEL DPLCAPMOD D (CJO = 0.5e-10 IS = 1e-30 N = 10 M = 0.55)
.MODEL MMEDMOD PMOS (VTO = -1.17 KP = 0.6 IS=1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 12.4)
.MODEL MSTROMOD PMOS (VTO = -1.45 KP = 1.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD PMOS (VTO = -0.99 KP = 0.05 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 124 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 5.5e-4 TC2 = -1e-7)
.MODEL RDRAINMOD RES (TC1 = 2.8e-3 TC2 = 4.9e-6)
.MODEL RSLCMOD RES (TC1 = 3.7e-3 TC2 = 7.8e-6)
.MODEL RSOURCEMOD RES (TC1 = 3e-3 TC2 = 5.2e-6)
.MODEL RVTHRESMOD RES (TC1 = 9e-4 TC2 = 3e-7)
.MODEL RVTEMPMOD RES (TC1 = -5.5e-4 TC2 = -1e-9)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.5 VOFF= 0.2)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.2 VOFF= 0.5)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.4 VOFF= -0.1)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.1 VOFF= 0.4)
.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
GATE
1
RLGATE
LGATE
rev January 2003
RGATE
9
DPLCAP
12
20
EVTEMP
S1A
S1B
CA
18
22
EGS
13
8
10
+
13
+
14
13
6
6
8
RSLC2
ESG
S2A
S2B
8
6
EVTHRES
+
15
EDS
+
19
8
CB
CIN
+
5
8
51
5
5
14
MSTRO
50
+
RDRAIN
51
RSLC1
ESLC
21
16
8
MMED
8
EBREAK
RSOURCE
DBREAK
MWEAK
17
RBREAK
RVTHRES
IT
17
18
+
11
7
18
19
+
22
RVTEMP
VBAT
RLSOURCE
RLDRAIN
LSOURCE
DBODY
LDRAIN
SOURCE
DRAIN
FDG6318PZ Rev. B
3
2