CY28547LFXCT Silicon Laboratories Inc, CY28547LFXCT Datasheet - Page 14

• Manufacturer Part Number: CY28547LFXCT
• Description: Clock Generators & Support Products CK505 Mobile System Clock
• Manufacturer: Silicon Laboratories Inc

Specifications of CY28547LFXCT

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI_STP# Assertion
The PCI_STP# signal is an active LOW input used for
synchronous stopping and starting the PCI outputs and SRC
outputs if they are set to be stoppable in SMbus while the rest
of the clock generator continues to function. The set-up time
for capturing PCI_STP# going LOW is 10 ns (t
Figure 9.) The PCIF clocks will not be affected by this pin if
their corresponding control bit in the SMBus register is set to
allow them to be free running. All stopped PCI outputs are
.....................Document #: 001-05103 Rev *B Page 14 of 24
CPUC(Free Running
CPUT(Free Running
CPUC(Stoppable)
CPUT(Stoppable)
CPUC(Free Running)
CPUT(Free Running)
CPU_STOP#
CPUC(Stoppable)
CPUT(Stoppable)
CPU_STOP#
SRC 100MHz
DOT96T
DOT96C
PCI_STP#
PD
Figure 8. CPU_STP# = Tri-state, CPU_PD = Tri-state, DOT_PD = Tri-state
PCI_F
PD
Figure 10. CPU_STP# = Driven, CPU_PD = Driven, DOT_PD = Driven
PCI
Tsu
Figure 9. PCI_STP# Assertion Waveform
SU
). (See
driven Low, SRC outputs are High/Low if set to driven and
Low/Low if set to tri-state.
PCI_STP# Deassertion
The deassertion of the PCI_STP# signal will cause all PCI and
stoppable PCIF clocks to resume running in a synchronous
manner within two PCI clock periods after PCI_STP# transi-
tions to a HIGH level
1.8mS
CY28547
1.8 ms