CY28547LFXCT Silicon Laboratories Inc, CY28547LFXCT Datasheet - Page 7

• Manufacturer Part Number: CY28547LFXCT
• Description: Clock Generators & Support Products CK505 Mobile System Clock
• Manufacturer: Silicon Laboratories Inc

Specifications of CY28547LFXCT

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Byte 4 Control Register 4 (continued)
Byte 5 Control Register 5
Byte 6 Control Register 6
.......................Document #: 001-05103 Rev *B Page 7 of 24
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Bit
3
2
1
0
@Pup
@Pup
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
@Pup
0
0
0
0
LCD_96_100M[T/C]
SRC[T/C][9:1]
RESERVED
RESERVED
DOT96[T/C]
CPU[T/C]2
CPU[T/C]1
CPU[T/C]0
CPU[T/C]2
CPU[T/C]1
CPU[T/C]0
CPU[T/C]2
CPU[T/C]1
CPU[T/C]0
SRC[T/C]
PCIF0
Name
Name
Name
SRC3
SRC2
SRC1
SRC0
LCD_96_100M[T/C] PWRDWN Drive Mode
0 = Driven in PWRDWN, 1 = Tri-state
DOT PWRDWN Drive Mode
0 = Driven in PWRDWN, 1 = Tri-state
RESERVED, Set = 0
RESERVED, Set = 0
Allow control of PCIF0 with assertion of SW and HW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of CPU[T/C]2 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
Allow control of CPU[T/C]1 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
Allow control of CPU[T/C]0 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
SRC[T/C] Stop Drive Mode
0 = Driven when PCI_STP# asserted
1 = Tri-state when PCI_STP# asserted
CPU[T/C]2 Stop Drive Mode
0 = Driven when CPU_STP# asserted
1 = Tri-state when CPU_STP# asserted
CPU[T/C]1 Stop Drive Mode
0 = Driven when CPU_STP# asserted
1 = Tri-state when CPU_STP# asserted
CPU[T/C]0 Stop Drive Mode
0 = Driven when CPU_STP# asserted
1 = Tri-state when CPU_STP# asserted
SRC[T/C][9:1] PWRDWN Drive Mode
0 = Driven when PD asserted
1 = Tri-state when PD asserted
CPU[T/C]2 PWRDWN Drive Mode
0 = Driven when PD asserted
1 = Tri-state when PD asserted
CPU[T/C]1 PWRDWN Drive Mode
0 = Driven when PD asserted
1 = Tri-state when PD asserted
CPU[T/C]0 PWRDWN Drive Mode
0 = Driven when PD asserted
1 = Tri-state when PD asserted
Allow control of SRC[T/C]3 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]2 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]1 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]0 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Description
Description
Description
CY28547