CYW256OXCT Silicon Laboratories Inc, CYW256OXCT Datasheet

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CYW256OXCT

Manufacturer Part Number
CYW256OXCT
Description
Clock Buffer SDRAM & DDR Output Buff, W256 datasheet
Manufacturer
Silicon Laboratories Inc
Datasheet

Specifications of CYW256OXCT

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Rev 1.0, November 25, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Features
Note:
1. Internal 100K pull-up resistors present on inputs marked with *. Design should not rely solely on internal pull-up resistor to set I/O pins HIGH.
• One input to 12 output buffer/drivers
• Supports up to 2 DDR DIMMs or 3 SDRAM DIMMS
• One additional output for feedback
• SMBus interface for individual output control
• Low skew outputs (< 100 ps)
• Supports 266 MHz and 333 MHz DDR SDRAM
• Dedicated pin for power management support
• Space-saving 28-pin SSOP package
SCLOCK
PWR_DWN#
Block Diagram
SEL_DDR
BUF_IN
SDATA
Powerdown
Decoding
VDD3.5_2.5
Control
SMBus
12 Output Buffer for 2 DDR and 3 SRAM DIMMS
&
Tel:(408) 855-0555
DDR4C_SDRAM9
DDR5T_SDRAM10
DDR5C_SDRAM11
DDR4T_SDRAM8
FBOUT
DDR0T_SDRAM0
DDR0C_SDRAM1
DDR1T_SDRAM2
DDR1C_SDRAM3
DDR2T_SDRAM4
DDR2C_SDRAM5
DDR3T_SDRAM6
DDR3C_SDRAM7
Functional Description
The W256 is a 3.3V/2.5V buffer designed to distribute
high-speed clocks in PC applications. The part has 12 outputs.
Designers can configure these outputs to support 3 unbuffered
standard SDRAM DIMMs and 2 DDR DIMMs. The W256 can
be used in conjunction with the W250-02 or similar clock
synthesizer for the VIA Pro 266 chipset.
The W256 also includes an SMBus interface which can enable
or disable each output clock. On power-up, all output clocks
are enabled (internal pull-up).
Fax:(408) 855-0550
DDR0C_SDRAM1
DDR1C_SDRAM3
DDR2C_SDRAM5
DDR0T_SDRAM0
DDR2T_SDRAM4
DDR1T_SDRAM2
*PWR_DWN#
VDD3.3_2.5
VDD3.3_2.5
VDD3.3_2.5
BUF_IN
FBOUT
GND
GND
Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Top View
SSOP
www.SpectraLinear.com
28
27
26
25
24
23
22
21
20
19
18
17
16
15
[1]
Page 1 of 7
SEL_DDR*
DDR5T_SDRAM10
DDR5C_SDRAM11
VDD3.3_2.5
GND
DDR4T_SDRAM8
DDR4C_SDRAM9
VDD3.3_2.5
GND
DDR3T_SDRAM6
DDR3C_SDRAM7
GND
SCLK
SDATA
W256

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CYW256OXCT Summary of contents

Page 1

Output Buffer for 2 DDR and 3 SRAM DIMMS Features • One input to 12 output buffer/drivers • Supports DDR DIMMs or 3 SDRAM DIMMS • One additional output for feedback • SMBus interface for individual ...

Page 2

Pin Summary Name Pins SEL_DDR 28 SCLK 16 SDATA 15 BUF_IN 10 FBOUT 1 PWR_DWN# 2 DDR[0:5]T_SDRAM 3, 7, 12, 19, 23, 27 [0,2,4,6,8,10] DDR[0:5]C_SDRAM 4, 8, 13, 18, 22, 26 [1,3,5,7,9, 11] VDD3.3_2 14, 21, 25 GND ...

Page 3

Serial Configuration Map • The Serial bits will be read by the clock driver in the following order: Byte 0 — Bits Byte 1 — Bits ...

Page 4

Maximum Ratings Supply Voltage to Ground Potential..................–0.5 to +7.0V DC Input Voltage (except BUF_IN)............ –0. Storage Temperature .................................. –65°C to +150°C Static Discharge Voltage............................................>2000V (per MIL-STD-883, Method 3015) [2] Operating Conditions Parameter V Supply Voltage DD3.3 V Supply ...

Page 5

Switching Characteristics Parameter Name [4] t DDR Rising Edge Rate 3d [4] t DDR Falling Edge Rate 4d [4] t Output to Output Skew 5 t Output t4o Output Skew for 6 [2] SDRAM t SDRAM Buffer HH Prop. ...

Page 6

Figure 1 shows the differential clock directly terminated by a 120 Ω resistor Device Out Under Test Out Figure 1. Differential Signal Using Direct Termination Resistor Layout Example Single Voltage +3.3V Supply or 2.5V Supply ...

Page 7

... W256H W256HT Lead Free CYW256OXC CYW256OXCT Package Drawings and Dimension 28-Lead (5.3 mm) Shrunk Small Outline Package O28 While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any cir- cuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in ...

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