SL28506BZI-2T Silicon Laboratories Inc, SL28506BZI-2T Datasheet - Page 15

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SL28506BZI-2T

Manufacturer Part Number
SL28506BZI-2T
Description
Clock Generators & Support Products CK505 v1.1 PCIe Gen2
Manufacturer
Silicon Laboratories Inc
Datasheet

Specifications of SL28506BZI-2T

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
SL28506-2
C P U _S T P #
C P U T
C P U C
Figure 4. CPU_STP# Assertion Waveform
CPU_STP# Deassertion
The deassertion of the CPU_STP# signal will cause all CPU
outputs that were stopped to resume normal operation in a
synchronous manner, synchronous manner meaning that no
short or stretched clock pulses will be produce when the clock
resumes. The maximum latency from the deassertion to active
outputs is no more than two CPU clock cycles.
CPU _STP#
CP UT
CP UC
CP UT Internal
CP UC Internal
Tdrive_C PU_STP#,10 ns>2 00 mV
CPU_STP# Deassertion Waveform
1.8mS
CPU_STOP#
PD#
CPUT(Free Running
CPUC(Free Running
CPUT(Stoppable)
CPUC(Stoppable)
DOT96T
DOT96C
CPU_STP# = Driven, CPU_PD = Driven, DOT_PD = Driven
Rev 1.3 June 18, 2008
Page 15 of 28

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