DS2155G/T&R Maxim Integrated Products, DS2155G/T&R Datasheet - Page 209
DS2155G/T&R
Manufacturer Part Number
DS2155G/T&R
Description
Network Controller & Processor ICs T1/E1/J1 Single-Chip gle-Chip Transceiver
Manufacturer
Maxim Integrated Products
Datasheet
1.DS2155L.pdf
(238 pages)
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Figure 35-3. Receive-Side Boundary Timing (Elastic Store Disabled)
Note 1: RCHBLK is programmed to block channel 24.
Note 2: Shown is RLINK/RLCLK in the ESF framing mode.
Figure 35-4. Receive-Side 1.544MHz Boundary Timing (Elastic Store
Enabled)
Note 1: RSYNC is in the output mode (IOCR1.4 = 0).
Note 2: RSYNC is in the input mode (IOCR1.4 = 1).
Note 3: RCHBLK is programmed to block channel 24.
RCHBLK 1
RCHBLK
RSYSCLK
RFSYNC
RCHCLK
RMSYNC
RCHCLK
RSYNC
RSYNC
RLINK 2
RLCLK
RSYNC
RSER
RCLK
RSIG
RSIG
RSER
2
1
3
CHANNEL 23
CHANNEL 23
CHANNEL 23
A
CHANNEL 23
A
B
B
C/A D/B
C/A D/B
LSB
LSB
MSB
MSB
209 of 238
CHANNEL 24
CHANNEL 24
CHANNEL 24
CHANNEL 24
A
A
B
B
C/A D/B
C/A D/B
LSB
LSB
F
F
MSB
MSB
CHANNEL 1
CHANNEL 1
CHANNEL 1
CHANNEL 1
A
A
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