28478G-18 Mindspeed Technologies, 28478G-18 Datasheet - Page 99

• Manufacturer Part Number: 28478G-18
• Description: Multichannel Synchronous Communications Controller 208-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of 28478G-18

• Package: 208BGA
• Maximum Data Rate: 32768 Kbps
• Transmission Media Type: Wire
• Power Supply Type: Analog
• Typical Supply Current: 250 mA
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3 V
• Maximum Operating Supply Voltage: 3.6 V

Table 5-12.
5.2.2.6
Each channel group can have two separate values for maximum message length: MAXFRM1 or MAXFRM2 (see
Table
depending on non-FCS mode or FCS16 or FCS32 support, respectively. Each receive channel either selects one
of these message length values or disables message length checking altogether.
The MAXSEL bit field (see
for received-message length checking. If MUSYCC receives a message exceeding the allowed maximum, the
current message processing is discontinued and terminates further transfer of data to shared memory. In addition,
a Receive Buffer Status Descriptor, corresponding to the partially received message, indicates a Long Message
error condition, and an interrupt descriptor is generated towards the host indicating the same error condition.
In the case of a short message (bit count less than 3 or 5 octets), data is not transferred into shared memory and is
discarded. In addition, an interrupt descriptor is generated towards the host, indicating the same error condition.
28478-DSH-002-E
Field
Bit
2:0
6
5
4
3
5-13). The maximum message length is 4,094 octets. The minimum message length is either 1, 3, or 5
PORTMD[2:0]
TSYNC_EDGE
RDAT_EDGE
TDAT_EDGE
Port Configuration Descriptor (2 of 2)
Name
RSVD
NOTE:
Message Length Descriptor
Preliminary Information / Mindspeed Proprietary and Confidential
Table 5-18, Channel Configuration
The equation that defines maximum message length without generating a LNG error is:
Maximum Message Length = MAXFRM – FCS where FCS = 2 bytes for HDLC-16 protocol
and FCS = 4 bytes for HDLC-32 protocol.
Value
5–7
0
1
0
1
0
1
0
0
1
2
3
4
Receiver Data—Falling Edge. RDAT input sampled in on falling edge of RCLK.
Receiver Data—Rising Edge.
Transmitter Frame Synchronization—Falling Edge. TSYNC input sampled in on falling edge of TCLK.
Transmitter Frame Synchronization—Rising Edge.
Transmitter Data—Falling Edge. TDAT output latched out on falling edge of TCLK.
Transmitter Data—Rising Edge.
Reserved.
T1 Mode—24 time slots and T1 signaling.
E1 Mode—32 time slots and E1 signaling.
2xE1 Mode—64 time slots and E1 signaling.
4xE1 Mode—128 time slots and E1 signaling.
Nx64 Mode. Frame synchronization flywheel disabled. COFA detection disabled. Every synchronization
signal assertion resets time slot counter to zero.
Reserved.
Mindspeed Technologies
Descriptor) selects which, if any, register is used
®
Description
Memory Organization
86