AD6600ASTZ Analog Devices Inc, AD6600ASTZ Datasheet - Page 4

• Manufacturer Part Number: AD6600ASTZ
• Description: ADC Single 20MSPS 11-Bit Parallel 44-Pin LQFP
• Manufacturer: Analog Devices Inc

Specifications of AD6600ASTZ

• Package: 44LQFP
• Resolution: 11 Bit
• Sampling Rate: 20000 KSPS
• Number Of Adcs: 1
• Number Of Analog Inputs: 2
• Digital Interface Type: Parallel
• Input Type: Voltage
• Signal To Noise Ratio: 59(Typ) dB
• Sample And Hold: Yes
• Polarity Of Input Voltage: Bipolar
• Number Of Bits: 11
• Sampling Rate (per Second): 20M
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 976mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 44-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD6600–SPECIFICATIONS
TIMING REQUIREMENTS AND SWITCHING SPECIFICATIONS
(AVCC = 5 V, DVCC = 3.3 V; ENC and ENC = 20 MSPS, Duty Cycle = 50%; T
Parameter
ENCODE/CLK2×
CLK2×/DATA (D10:0, RSSI2:0)
CLK2×/AB_OUT
ENCODE/DATA (D10:0, RSSI2:0)
ENCODE/AB_OUT
NOTES
1
2
3
4
5
6
Specifications subject to change without notice.
All switching specifications tested by driving ENC and ENC differentially.
See AD6600 Timing Diagrams.
This specification IS NOT a function of Encode period and duty cycle.
This specification IS a function of Encode period and duty cycle.
CLK2× referenced to 2.0 V crossing; digital output levels referenced to 0.8 V and 2.0 V crossings; all outputs with 10 pF load.
For these particular specifications, the 25°C specification is valid from 25°C to 85°C. The Full temperature specification includes cold temperature extreme and
covers the entire range, –40°C to +85°C.
Encode Rising to CLK2× Falling
Encode Rising to CLK2× Rising
CLK2× to DATA Rising Low Delay
CLK2× to DATA Hold Time
CLK2× to DATA Falling Low
CLK2× to DATA Setup Time
CLK2× to AB_OUT Rising Low Delay
CLK2× to AB_OUT Hold Time
CLK2× to AB_OUT Falling Low Delay
CLK2× to AB_OUT Setup Time
ENCODE to DATA Rising Low Delay
ENCODE to DATA Hold Time
ENCODE to DATA Falling Low Delay
ENCODE to DATA Delay (Setup)
ENCODE to AB_OUT Rising Low Delay
ENCODE to AB_OUT Delay (Hold)
ENCODE to AB_OUT Falling Low Delay
ENCODE to AB_OUT Delay (Setup)
@ Encode = 13 MSPS, 50% Duty Cycle
@ Encode = 20 MSPS, 50% Duty Cycle
@ Encode = 13 MSPS, 50% Duty Cycle
@ Encode = 20 MSPS, 50% Duty Cycle
@ Encode = 13 MSPS, 50% Duty Cycle
@ Encode = 20 MSPS, 50% Duty Cycle
@ Encode = 13 MSPS, 50% Duty Cycle
@ Encode = 20 MSPS, 50% Duty Cycle
@ Encode = 13 MSPS, 50% Duty Cycle
@ Encode = 20 MSPS, 50% Duty Cycle
@ Encode = 13 MSPS, 50% Duty Cycle
@ Encode = 20 MSPS, 50% Duty Cycle
@ Encode = 13 MSPS, 50% Duty Cycle
@ Encode = 20 MSPS, 50% Duty Cycle
5
3
4
3, 6
5
4
3
4
3
4
4
3
4
4
3
4
3, 6
4
4
4
6
6
6
6
Name
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CF
CR
2×_DRL
H_D2×
2×_DFL
S_D2×
2×_ARL
H_A2×
2×_AFL
S_A2×
EN_DRL
H_DEN
EN_DFL
S_DEN
EN_ARL
H_AEN
EN_AFL
S_AEN
Temp
Full
Full
Full
Full
Full
Full
25°C
Full
Full
Full
25°C
Full
Full
Full
25°C
Full
Full
Full
25°C
Full
Full
Full
Full
Full
Full
Full
Full
25°C
Full
Full
Full
Full
Full
Full
Full
Full
25°C
Full
MIN
= –40 C, T
Test
Level
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
MAX
= +85 C unless otherwise noted.)
1, 2
Min
6.5
25.7
19.0
3.0
3.0
10.0
11.0
16.5
5.0
3.0
7.0
7.0
12.0
10.7
12.5
2.0
–1.0
28.7
22.0
26.2
8.0
6.0
32.7
26.0
22.2
5.0
2.0
AD6600AST
Typ
8.0
t
27.2
20.5
6.5
6.5
15.0
15.5
t
23.0
CF
ENCH
10.0
9.5
11.0
11.0
18.0
19.0
t
19.5
7.0
6.0
t
t
33.7
27.0
t
t
34.2
14.5
14.0
t
t
38.2
31.5
t
t
30.7
11.5
10.5
ENCH
CR
EN_DRL
CR
ENC
CR
EN_ARL
CR
ENC
+ (t
+ t
+ t
+ t
+ t
– t
– t
– t
– t
ENCH
2×_DRL
2×_DFL
2×_ARL
2×_AFL
EN_DFL
EN_AFL
2×_DFL
2×_AFL
)/2
Max
9.5
28.7
22.0
20.0
22.0
23.0
26.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns