XC2VP7-5FF672C Xilinx Inc, XC2VP7-5FF672C Datasheet - Page 6

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XC2VP7-5FF672C

Manufacturer Part Number
XC2VP7-5FF672C
Description
FPGA Virtex-II Pro™ Family 11088 Cells 1050MHz 0.13um/90nm (CMOS) Technology 1.5V 672-Pin FCBGA
Manufacturer
Xilinx Inc
Datasheet

Specifications of XC2VP7-5FF672C

Package
672FCBGA
Family Name
Virtex-II Pro™
Device Logic Units
11088
Number Of Registers
9856
Maximum Internal Frequency
1050 MHz
Typical Operating Supply Voltage
1.5 V
Maximum Number Of User I/os
396
Ram Bits
811008

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The DCI I/O feature automatically provides on-chip termina-
tion for each single-ended I/O standard.
The IOB elements also support the following differential sig-
naling I/O standards:
Two adjacent pads are used for each differential pair. Two or
four IOBs connect to one switch matrix to access the routing
resources. On-chip differential termination is available for
LVDS, LVDS Extended, ULVDS, and LDT standards.
Configurable Logic Blocks (CLBs)
CLB resources include four slices and two 3-state buffers.
Each slice is equivalent and contains:
The function generators F & G are configurable as 4-input
look-up tables (LUTs), as 16-bit shift registers, or as 16-bit
distributed SelectRAM+ memory.
In addition, the two storage elements are either
edge-triggered D-type flip-flops or level-sensitive latches.
Each CLB has internal fast interconnect and connects to a
switch matrix to access general routing resources.
Block SelectRAM+ Memory
The block SelectRAM+ memory resources are 18 Kb of
True Dual-Port RAM, programmable from 16K x 1 bit to
512 x 36 bit, in various depth and width configurations.
Each port is totally synchronous and independent, offering
three "read-during-write" modes. Block SelectRAM+ mem-
ory is cascadable to implement large embedded storage
blocks. Supported memory configurations for dual-port and
single-port modes are shown in
Table 2: Dual-Port and Single-Port Configurations
18 X 18 Bit Multipliers
A multiplier block is associated with each SelectRAM+
memory block. The multiplier block is a dedicated
18 x 18-bit 2s complement signed multiplier, and is opti-
DS083 (v4.7) November 5, 2007
Product Specification
HSTL (1.5V and 1.8V, Class I, II, III, and IV)
SSTL (1.8V and 2.5V, Class I and II)
LVDS and Extended LVDS (2.5V)
BLVDS (Bus LVDS)
ULVDS
LDT
LVPECL (2.5V)
Two function generators (F & G)
Two storage elements
Arithmetic logic gates
Large multiplexers
Wide function capability
Fast carry look-ahead chain
Horizontal cascade chain (OR gate)
16K x 1 bit
8K x 2 bits
R
4K x 4 bits
2K x 9 bits
Table
2.
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Introduction and Overview
512 x 36 bits
1K x 18 bits
www.xilinx.com
mized for operations based on the block SelectRAM+ con-
tent on one port. The 18 x 18 multiplier can be used
independently
Read/multiply/accumulate operations and DSP filter struc-
tures are extremely efficient.
Both the SelectRAM+ memory and the multiplier resource
are connected to four switch matrices to access the general
routing resources.
Global Clocking
The DCM and global clock multiplexer buffers provide a
complete solution for designing high-speed clock schemes.
Up to twelve DCM blocks are available. To generate
deskewed internal or external clocks, each DCM can be
used to eliminate clock distribution delay. The DCM also
provides 90-, 180-, and 270-degree phase-shifted versions
of its output clocks. Fine-grained phase shifting offers
high-resolution phase adjustments in increments of
the clock period. Very flexible frequency synthesis provides
a clock output frequency equal to a fractional or integer mul-
tiple of the input clock frequency. For exact timing parame-
ters, see
DC and Switching
Virtex-II Pro devices have 16 global clock MUX buffers, with
up to eight clock nets per quadrant. Each clock MUX buffer
can select one of the two clock inputs and switch glitch-free
from one clock to the other. Each DCM can send up to four
of its clock outputs to global clock buffers on the same edge.
Any global clock pin can drive any DCM on the same edge.
Routing Resources
The IOB, CLB, block SelectRAM+, multiplier, and DCM ele-
ments all use the same interconnect scheme and the same
access to the global routing matrix. Timing models are
shared, greatly improving the predictability of the perfor-
mance of high-speed designs.
There are a total of 16 global clock lines, with eight available
per quadrant. In addition, 24 vertical and horizontal long
lines per row or column, as well as massive secondary and
local
Virtex-II Pro buffered interconnects are relatively unaffected
by net fanout, and the interconnect layout is designed to
minimize crosstalk.
Horizontal and vertical routing resources for each row or
column include:
Boundary Scan
Boundary-scan instructions and associated data registers
support a standard methodology for accessing and config-
uring Virtex-II Pro devices, complying with IEEE standards
1149.1 and 1532. A system mode and a test mode are
24 long lines
120 hex lines
40 double lines
16 direct connect lines (total in all four directions)
routing
Virtex-II Pro and Virtex-II Pro X Platform FPGAs:
of
resources,
Characteristics.
the
block
provide
SelectRAM+
fast
interconnect.
Module 1 of 4
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