XC2VP7-5FF672C Xilinx Inc, XC2VP7-5FF672C Datasheet - Page 8

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XC2VP7-5FF672C

Manufacturer Part Number
XC2VP7-5FF672C
Description
FPGA Virtex-II Pro™ Family 11088 Cells 1050MHz 0.13um/90nm (CMOS) Technology 1.5V 672-Pin FCBGA
Manufacturer
Xilinx Inc
Datasheet

Specifications of XC2VP7-5FF672C

Package
672FCBGA
Family Name
Virtex-II Pro™
Device Logic Units
11088
Number Of Registers
9856
Maximum Internal Frequency
1050 MHz
Typical Operating Supply Voltage
1.5 V
Maximum Number Of User I/os
396
Ram Bits
811008

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Virtex-II Pro / Virtex-II Pro X Device/Package Combinations and Maximum I/Os
Offerings include ball grid array (BGA) packages with
1.0 mm pitch. In addition to traditional wire-bond intercon-
nect (FG/FGG packages), flip-chip interconnect (FF pack-
ages) is used in some of the BGA offerings. Flip-chip
interconnect construction supports more I/Os than are pos-
sible in wire-bond versions of similar packages, providing a
high pin count and excellent power dissipation.
The device/package combination table
maximum number of user I/Os and RocketIO / RocketIO X
MGTs for each device and package using wire-bond or
flip-chip technology.
Table 3: Virtex-II Pro Device/Package Combinations and Maximum Number of Available I/Os
Maximum Performance
Maximum performance of the RocketIO / RocketIO X transceiver and the PowerPC processor block varies, depending on
package style and speed grade. See
Characteristics
Table 4: Maximum RocketIO / RocketIO X Transceiver and Processor Block Performance
DS083 (v4.7) November 5, 2007
Product Specification
Notes:
1.
2.
3.
Notes:
1.
2.
3.
Pitch (mm)
RocketIO X Transceiver FlipChip (FF)
RocketIO Transceiver FlipChip (FF)
RocketIO Transceiver Wirebond (FG)
PowerPC Processor Block
Package
XC2VPX20
XC2VPX70
XC2VP100
Size (mm)
XC2VP20
XC2VP30
XC2VP40
XC2VP50
XC2VP70
XC2VP2
XC2VP4
XC2VP7
Wirebond packages FG256, FG456, and FG676 are also available in Pb-free versions FGG256, FGG456, and FGG676. See
Examples
Virtex-II Pro X device is equipped with RocketIO X transceiver cores.
The RocketIO transceivers in devices in the FF1148 and FF1696 packages are not bonded out to the package pins.
-7 speed grade devices are not available in Industrial grade.
IMPORTANT! When CPMC405CLOCK runs at speeds greater than 350 MHz in -7 Commercial grade dual-processor devices, or greater than
300 MHz in -6 Industrial grade dual-processor devices, users must implement the technology presented in XAPP755, “PowerPC 405 Clock Macro for
-7(C) and -6(I) Speed Grade Dual-Processor Devices.” Refer to
XC2VPX70 is only available at fixed 4.25 Gb/s baud rate.
(1)
R
for details on how to order.
FGG256
FG256/
17 x 17
140 / 4
140 / 4
contains the rest of the FPGA fabric performance parameters.
1.00
Device
FGG456
FG456/
23 x 23
156 / 4
248 / 4
248 / 8
1.00
FG676
26 x 26
404 / 8
416 / 8
416 / 8
Table 4
1.00
(Table
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Introduction and Overview
for details.
3) details the
27 x 27
FF672
204 / 4
348 / 4
396 / 8
1.00
3.125
400
N/A
2.5
-7
www.xilinx.com
(1)
(2)
Table 1
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching
31 x 31
FF896
396 / 8
556 / 8
552 / 8
556 / 8
1.00
to identify dual-processor devices.
The FF1148 and FF1696 packages have no RocketIO
transceivers bonded out. Extra SelectIO-Ultra resources
occupy available pins in these packages, resulting in a
higher user I/O count. These packages are available for the
XC2VP40, XC2VP50, and XC2VP100 devices only.
The I/Os per package count includes all user I/Os except
the 15 control pins (CCLK, DONE, M0, M1, M2, PROG_B,
PWRDWN_B, TCK, TDI, TDO, TMS, HSWAP_EN, DXN,
DXP, and RSVD), VBATT, and the RocketIO / RocketIO X
transceiver pins.
(2)
Speed Grade
FF1152
35 x 35
692 / 12
692 / 16
564 / 8
644 / 8
1.00
3.125
6.25
350
2.5
-6
(2)
(3)
FF1148
35 x 35
804 / 0
812 / 0
1.00
(3)
(3)
FF1517
852 / 16
964 / 16
40 x 40
4.25
300
2.0
2.0
1.00
-5
(3)
42.5 x 42.5
1,040 / 20
FF1704
996 / 20
992 / 20
1.00
Virtex-II Pro Ordering
(2)
Units
Gb/s
Gb/s
Gb/s
MHz
Module 1 of 4
42.5 x 42.5
1,164 / 0
FF1696
1.00
(3)
7

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