PE43404MLI-Z Peregrine Semiconductor, PE43404MLI-Z Datasheet
PE43404MLI-Z
Specifications of PE43404MLI-Z
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PE43404MLI-Z Summary of contents
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... Typical DC DC ≤ 1.2 GHz - 1.4 DC ≤ 1.2 GHz - - 1 MHz ≤ 1.2 GHz MHz ≤ 1.2 GHz - 52 DC ≤ 1.2 GHz ©2008 Peregrine Semiconductor Corp. All rights reserved. Maximum Units 2000 MHz 1.95 dB ±(0.25 atten setting dBm - dBm - dB µs 1 Page ...
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... See “Resistor on 3” paragraph Exposed Solder Pad Connection The exposed solder pad on the bottom of the package must be grounded for proper device operation. ©2008 Peregrine Semiconductor Corp. All rights reserved. Page Table 3. Absolute Maximum Ratings Symbol V C8 ...
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... R23 10K DATA 3 DATA CLK 4 CLK J19 15 C8 Z=75 Ohm SMA R24 0 OHM 14 1 RFOUT MLPQ4X4 12 -VDD or GND VNEG GND 11 C14 C12 100pF 0.1µF VDD C10 C9 100pF 0.1µF ©2008 Peregrine Semiconductor Corp. All rights reserved. J20 SUPPLY VDD Page ...
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... Figure 8. Input Return Loss at Major Attenuation Steps (Zo=75 ohms -10 -15 -20 8dB -25 15dB -30 0 500 1000 RF Frequency (MHz) ©2008 Peregrine Semiconductor Corp. All rights reserved. Page 3 Figure 7. Attenuation at Major steps -40C 25C 85C 1500 2000 Figure 9. Output Return Loss at Major 4dB 1500 2000 Product Specification ...
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... Figure 11. Attenuation Error Vs. Attenuation 1 0.5 8dB 0 15dB -0.5 -1 1500 2000 Figure 13. Input 1 dB Compression (Zo=50 ohms 1500 2000 ©2008 Peregrine Semiconductor Corp. All rights reserved. Setting Attenuation Setting (dB) 0 500 1000 1500 RF Frequency (MHz) 10Mhz 250Mhz 500Mhz 750Mhz 1010Mhz 1210Mhz 14 16 ...
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... Attenuation Setting (dB) Note: Positive attenuation error indicates higher attenuation than target value ©2008 Peregrine Semiconductor Corp. All rights reserved. Page 3 Figure 15. Attenuation Error Vs. Attenuation 10MHz, 85C Figure 17. Attenuation Error Vs. Attenuation 0.4 0.3 0.2 1000MHz, -40C ...
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... Table 6 (Power-Up Truth Table, Parallel 2 dB Mode Table 6. Power-Up Truth Table, Parallel 15 dB Interface Mode P Note: LE PUP2 Attenuation State 0 Reference Loss Defined by C1-C8 X Power up with LE=1 provides normal parallel operation with C1-C8, and PUP2 is not active. ©2008 Peregrine Semiconductor Corp. All rights reserved. Page ...
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... Note verified during the functional pattern test. Serial Clk programming sections of the functional pattern are clocked at 10 MHz to verify fclk specification. ©2008 Peregrine Semiconductor Corp. All rights reserved. Page Table 7. 4-Bit Attenuator Serial Programming Register Map B5 0 ↑ ...
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... Coplanarity applies to the exposed heat sink slug as well as the terminals. 3. Dimensions are in millimeters. Document No. 70-0258-02 │ www.psemi.com 4.00 2.00 INDEX AREA - B - 2.00 X 2.00 0.25 C 0.10 C 0.08 C 2.00 1. DETAIL A 0. SEATING - C - PLANE EXPOSED PAD 2 0. ©2008 Peregrine Semiconductor Corp. All rights reserved. Page ...
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... Figure 21. Marking Specifications Figure 22. Tape and Reel Drawing Table 10. Ordering Information Order Code Part Marking PE43404MLI 43404 PE43404MLI-Z 43404 EK43404-01 PE43404-EK ©2008 Peregrine Semiconductor Corp. All rights reserved. Page 43404 YYWW ZZZZZ YYWW = Date Code ZZZZZ = Last five digits of PSC Lot Number ...
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... Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, and UTSi are registered trademarks and UltraCMOS and HaRP are trademarks of Peregrine Semiconductor Corp. ©2008 Peregrine Semiconductor Corp. All rights reserved. Page ...