MMCCMB2107 Freescale, MMCCMB2107 Datasheet - Page 229

• Manufacturer Part Number: MMCCMB2107
• Manufacturer: Freescale

Specifications of MMCCMB2107

• Lead Free Status / RoHS Status: Not Compliant

MMC2107 – Rev. 2.0
MOTOROLA
NOTE:
NOTE:
NOTE:
RFD[2:0] — Reduced Frequency Divider Field
In external clock mode, the RFD[2:0] bits have no effect.
See
LOCEN — Loss of Clock Enable Bit
In external clock mode, the LOCEN bit has no effect.
DISCLK — Disable CLKOUT Bit
FWKUP — Fast Wakeup Bit
When FWKUP = 0, if the PLL or OSC is enabled and unintentionally lost
in stop mode, the PLL wakes up in self-clocked mode or reference clock
mode depending on the clock that was lost.
In external clock mode, the FWKUP bit has no effect on the wakeup
sequence.
The binary value written to RFD[2:0] is the PLL frequency divisor. See
Table
relock delay. Changes in clock frequency are synchronized to the
next falling edge of the current system clock. To avoid surpassing the
allowable system operating frequency, write to RFD[2:0] only when
the LOCK bit is set.
The LOCEN bit enables the loss of clock function. LOCEN does not
affect the loss of lock function.
The DISCLK bit determines whether CLKOUT is driven. Setting the
DISCLK bit holds CLKOUT low.
The FWKUP bit determines when the system clocks are enabled
during wakeup from stop mode.
Freescale Semiconductor, Inc.
Table
For More Information On This Product,
1 = Loss of clock function enabled
0 = Loss of clock function disabled
1 = CLKOUT disabled
0 = CLKOUT enabled
1 = System clocks enabled on wakeup regardless of PLL lock
0 = System clocks enabled only when PLL is locked or operating
10-3. Changing RFD[2:0] does not affect the PLL or cause a
status
normally
10-6.
Go to: www.freescale.com
Clock Module
Memory Map and Registers
Technical Data
Clock Module
229