KSZ8864RMN Micrel Inc, KSZ8864RMN Datasheet - Page 11
KSZ8864RMN
Manufacturer Part Number
KSZ8864RMN
Description
IC ETHERNET SW 4PORT 64QFN
Manufacturer
Micrel Inc
Datasheet
1.KSZ8864RMN.pdf
(112 pages)
Specifications of KSZ8864RMN
Controller Type
Ethernet Switch Controller
Interface
MII, RMII
Voltage - Supply
1.8V, 2.5V, 3.3V
Operating Temperature
0°C ~ 70°C
Mounting Type
*
Package / Case
*
Lead Free Status / RoHS Status
Supplier Unconfirmed
Current - Supply
-
Lead Free Status / RoHS Status
Supplier Unconfirmed, Lead free / RoHS Compliant
Other names
576-3787
KSZ8864RMN
KSZ8864RMN
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
KSZ8864RMNI
Manufacturer:
MICREL
Quantity:
7 143
Company:
Part Number:
KSZ8864RMNUB
Manufacturer:
MICREL
Quantity:
101
Micrel, Inc.
KSZ8864RMN
List of Figures
Figure 1. Typical Straight Cable Connection ............................................................................................................... 24
Figure 2. Typical Crossover Cable Connection ........................................................................................................... 25
Figure 3. Auto-Negotiation ........................................................................................................................................... 26
Figure 4. Destination Address Lookup Flow Chart, Stage 1 ........................................................................................ 30
Figure 5. Destination Address Resolution Flow Chart – Stage 2................................................................................. 31
Figure 6. 802.1p Priority Field Format.......................................................................................................................... 37
Figure 7. Tail Tag Frame Format .................................................................................................................................. 39
Figure 8. KSZ8864RMN EEPROM Configuration Timing Diagram ............................................................................. 43
Figure 9. SPI Write Data Cycle .................................................................................................................................... 44
Figure 10. SPI Read Data Cycle .................................................................................................................................. 44
Figure 11. SPI Multiple Write ....................................................................................................................................... 45
Figure 12. SPI Multiple Read ....................................................................................................................................... 45
Figure 13. EEPROM Interface Input Receive Timing Diagram.................................................................................. 101
Figure 14. EEPROM Interface Output Transmit Timing Diagram .............................................................................. 101
Figure 15. MAC Mode MII Timing – Data Received from MII ..................................................................................... 102
Figure 16. MAC Mode MII Timing – Data Transmitted from MII ................................................................................. 102
Figure 17. PHY Mode MII Timing – Data Received from MII...................................................................................... 103
Figure 18. PHY Mode MII Timing – Data Transmitted from MII.................................................................................. 103
Figure 19. RMII Timing – Data Received from RMII .................................................................................................. 104
Figure 20. RMII Timing – Data Transmitted to RMII .................................................................................................. 104
Figure 21. SPI Input Timing ....................................................................................................................................... 105
Figure 22. SPI Output Timing..................................................................................................................................... 106
Figure 23: Auto-Negotiation Timing ........................................................................................................................... 107
Figure 24. MDC/MDIO Timing.................................................................................................................................... 108
Figure 25. Reset Timing ............................................................................................................................................. 109
Figure 26. Recommended Reset Circuit .................................................................................................................... 110
Figure 27. Recommended Circuit for Interfacing with CPU/FPGA Reset.................................................................. 110
11
January 2011
M9999-012011-1.2