82P2821BH IDT, Integrated Device Technology Inc, 82P2821BH Datasheet - Page 100
82P2821BH
Manufacturer Part Number
82P2821BH
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.82P2821BH.pdf
(151 pages)
Specifications of 82P2821BH
Number Of Transceivers
1
Screening Level
Industrial
Mounting
Surface Mount
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Lead Free Status / RoHS Status
Not Compliant
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PG - Pattern Generation Control Register
Address: 010H, 050H, 090H, 0D0H, 110H, 150H, 190H, 1D0H, (CH1~CH8)
Type: Read / Write
Default Value: 00H
Programming Information
IDT82P2821
5 - 4
1 - 0
Bit
7
6
3
2
210H, 250H, 290H, 2D0H, 310H, 350H, 390H, 3D0H, (CH9~CH16)
410H, 450H, 490H, 4D0H, 510H, (CH17~CH21)
7D0H (CH0)
7
-
PRBG_SEL[1:0] These bits are valid only when the PRBS pattern is generated. They select the PRBS pattern.
PG_EN[1:0]
PAG_INV
PG_POS
PG_CK
Name
-
PG_CK
6
Reserved.
This bit selects the reference clock when the pattern (including PRBS, ARB & IB) is generated.
When the pattern is generated in the receive path:
0: XCLK. (default)
1: Recovered clock from the received signal.
When the pattern is generated in the transmit path:
0: XCLK. (default)
1: Transmit clock, i.e., the clock input on TCLKn (in Transmit Single Rail NRZ Format mode and in Transmit Dual Rail NRZ For-
mat mode) or the clock recovered from the data input on TDPn and TDNn (in Transmit Dual Rail RZ Format mode)
These bits select the pattern to be generated.
00: Disable. (default)
01: PRBS.
10: ARB.
11: IB.
This bit selects the pattern (including PRBS, ARB & IB) generation direction.
0: Transmit path. (default)
1: Receive path.
This bit controls whether to invert the generated PRBS/ARB pattern.
0: Normal. (default)
1: Invert.
00: 2
01: 2
1X: 2
20
15
11
- 1 QRSS. (default)
- 1 PRBS.
- 1 PRBS.
PG_EN1
5
PG_EN0
4
21(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
100
PG_POS
3
Description
PAG_INV
2
PRBG_SEL1
1
February 6, 2009
PRBG_SEL0
0
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