PEF2256EV22NP Lantiq, PEF2256EV22NP Datasheet - Page 193

PEF2256EV22NP

Manufacturer Part Number
PEF2256EV22NP
Description
Manufacturer
Lantiq
Datasheet

Specifications of PEF2256EV22NP

Number Of Transceivers
1
Screening Level
Industrial
Mounting
Surface Mount
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Lead Free Status / RoHS Status
Supplier Unconfirmed
FS/DL data on system transmit highway (XDI), time slot 0:
Figure 74
7.5.2.1
The pulse length of SYPR and RFM is always the basic T1/J1 bit width (648 ns) in
1.544-MHz mode or the E1 bit width (488 ns) in 2.048-MHz mode.
This chapter describes the system highway operation in 1.544-MHz mode only. If the
system highway is operated in 2.048-MHz mode, the description given in
Chapter 6.5.2.1
SYPX Offset Calculation
T:
BF:
SC:
X:
0
5
Data Sheet
T
T
4:
T
Time between the active edge of SCLKX after SYPX pulse begin and beginning
of the next frame (F-bit, channel phase 0), measured in number of SCLKX clock
intervals; maximum delay: T
Basic frequency; 1.544 Mbit/s
System clock rate; 1.544, 3.088, 6.176, or 12.352 MHz
Programming value to be written to registers RC0 and RC1 (see
max
Transmit Offset Programming
: X = (200
Transmit FS/DL Bits on XDI (T1/J1)
X = 3 - T + (7
on
Page 122
MSB
1
SC/BF) - T + 3
2
SC/BF)
applies.
3
max
FS/DL Time-Slot
= (200
4
193
5
SC/BF) - (7
6
Functional Description T1/J1
7
FS/DL
LSB
8
SC/BF) - 1
FS/DL Data Bit
Rev. 1.1, 2005-06-13
PEF 2256 H/E
ITD06460
Page
FALC
381).
®
56

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