PEF2256EV22NP Lantiq, PEF2256EV22NP Datasheet - Page 425

• Manufacturer Part Number: PEF2256EV22NP
• Manufacturer: Lantiq

Specifications of PEF2256EV22NP

• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Supplier Unconfirmed

HRAC3
DIV3
HDLCI3
Global Clock Mode Register 1 (Read/Write)
Value after reset: 00
GCM1
See
Global Clock Mode Register 2 (Read/Write)
Value after reset: 00
GCM2
Data Sheet
Table 73
7
7
for programming.
101 One-byte address comparison mode (RAH1, 2)
110 Reserved
111 No HDLC framing mode 1
Receiver Active - HDLC Channel 3
Switches the HDLC channel 3 receiver to operational or inoperational
state.
0
1
Data Inversion - HDLC Channel 3
Setting this bit will invert the internal generated HDLC channel 3 data
stream.
0
1
Inverse HDLC Operation - HDLC Channel 3
Setting this bit selects the HDLC channel 3 operation mode.
0
1
H
H
Receiver inactive
Receiver active
Normal operation, HDLC data stream not inverted
HDLC channel 3 data stream inverted
Normal operation, HDLC attached to line side
Inverse operation, HDLC attached to system side.
HDLC data is received on XDI and transmitted on RDO.
GCM1(7:0)
GCM2(7:0
425
Rev. 1.1, 2005-06-13
T1/J1 Registers
PEF 2256 H/E
0
0
FALC
(93)
(92)
®
56