NSK70721PE.C2 Intel, NSK70721PE.C2 Datasheet - Page 12

• Manufacturer Part Number: NSK70721PE.C2
• Manufacturer: Intel

Specifications of NSK70721PE.C2

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Lead Free Status / RoHS Status: Supplier Unconfirmed

SK70725/SK70721 — Enhanced Multi-Rate DSL Data Pump Chip Set
12
1. This input is a Schmidt Triggered circuit and includes an internal pull-up device.
2. This input is a Schmidt Triggered circuit and includes an internal pull-down device.
3. This input includes an internal pull-up device.
4. This input includes an internal pull-down device.
5. I/O column entries: DI = Digital Input; DO = Digital Output; DI/O = Digital Input/Output; AI = Analog Input; AO = Analog Output;
Indication
Clock and
IAFE I/F
Control
AI/O = Analog Input/Output; S = Supply.
Status
Group
Select
Mode
Table 2.
Pin #
EDSP Pin Assignments/Signal Descriptions (Continued)
16
15
29
31
30
14
13
19
20
21
22
23
24
25
26
27
SLAVE_CLK
MSTR_CLK
SRCTL_FS
MODE_S1
MODE_S2
MODE_S3
VCO_CLK
AGC_SET
SER_CTL
MASTER
TX_CLK
Symbol
ACTIVE
TMAG
TSGN
AD0
AD1
I/O
DI
DI
DI
DI
DO
DI
DO
DO
DO
DI
DI
DI
DO
DO
DO
DI
DI
3
3
3
3
1
4
4
4
5
Master. When MASTER is high, the Data Pump operates in Master mode and is
the link timing source. When MASTER is low, the Data Pump operates in Slave
mode. The EDSP must be reset after the state of MASTER is changed. Pulled
high internally.
Mode Select 1.
Mode Select 2.
Mode Select 3.
Link Active Indicator. In operating modes 0, 1, 2, 4, and 5, ACTIVE is asserted
whenever the EMDP completes the Activation process. In operating modes 6
and 7, ACTIVE is asserted on detection of two consecutive frame
synchronization words. ACTIVE goes high if signal is lost or the frame
synchronization word is not detected in six consecutive frames.
Slave Mode Reference Clock. Master clock for Slave Mode, at 16 times the line
rate. This clock is used as a reference clock until the clock is recovered from the
received signal. Tie high or low in Master Mode.
MDSL Reference Clock. In Master Mode, this input clock, at 16 times the line
rate, generates transmit and receive timing.
In Slave Mode, this output is designed to drive the MSTR_CLK input of another
Data Pump configured as a repeater.
Receive Clock Input. A replica of the clock generated by the IAFE VCXO which
is provided to the EDSP. It is 32 times the line rate.
Serial Control Output.
Serial control frame strobe signal. Equal to Receive Baud Rate and derived
from VCO_CLK.
Analog to Digital Converter Data Line 0.
Analog to Digital Converter Data Line 1.
AGC Adjust Input.
Transmit Symbol Clock. Four times the line rate.
Transmit Quat Magnitude Bit.
Transmit Quat Sign Bit.
Together determine the framing and data interface mode of
the EMDP. See
Description
Table
5.
Datasheet