NSK70721PE.C2 Intel, NSK70721PE.C2 Datasheet - Page 17

• Manufacturer Part Number: NSK70721PE.C2
• Manufacturer: Intel

Specifications of NSK70721PE.C2

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Lead Free Status / RoHS Status: Supplier Unconfirmed

3.0
3.1
3.1.1
3.1.1.1
3.1.1.2
Datasheet
Functional Description
The Enhanced MDSL Data Pump (EMDP) chip set provides synchronous, full duplex data
transport on a single twisted wire pair using 2B1Q line coding and echo cancellation. The EMDP
provides symmetrical data transport at any line rate from 272 to 1,168 kbps. This document
specifies performance at a few typical line rates, but all line rates between 272 and 1168 kbps are
allowed. The EMDP includes an internal state machine and can activate and operate without a
processor. The EMDP can transport data which is synchronous, asynchronous, or near-
synchronous (pleisiochronous) to the line rate of the Data Pump. Several new features have been
added in the EDSP chip as compared to previous MDSP and HDX - SK70720, SK70706,
SK70708, and SK70707. This chapter provides component description, Data Pump operation, and
special features.
Component Description
The EMDP chip set consists of the IAFE chip and EDSP chip. The following paragraphs describe
the chip set components with reference to internal functions and their interfaces.
Integrated Analog Front End
The Integrated Analog Front End (IAFE) incorporates the following analog functions:
The IAFE provides the complete analog front end for the EMDP. It includes transmit pulse
shaping, line driver, receive A/D converter, and the VCO portion of the receiver PLL function.
Transmit and receive control signals are exchanged between IAFE and EDSP through a serial port.
The IAFE line interface uses a single twisted pair line for both transmit and receive.
Table 1
specifications.
IAFE Transmitter
The IAFE transmitter performs 2B1Q coding, pulse shaping and driving functions. It generates a
shaped output pulse at the baud rate and has one of four levels determined by TMAG and TSGN.
Refer to Test Specifications for frequency and voltage of the pulse templates. Following is a
description of 2B1Q line coding.
2B1Q Line Code
The 2B1Q line code utilized in the EMDP is same as that selected by ANSI and ETSI as the
preferred line code for ISDN BRA and HDSL applications. This line code provides good
performance at minimum complexity. The line code utilizes pulse amplitude modulation to encode
two data bits (2B) into a single amplitude modulated pulse. The pulse amplitude is restricted to one
of four (quaternary) levels. This pulse is familiarly known as a “quat” and gives the second part of
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transmit driver
transmit and receive filters
Phase-Locked Loop (PLL)
analog-to-digital converter
lists the IAFE pin descriptions. Refer to Test Specifications for IAFE electrical and timing
Enhanced Multi-Rate DSL Data Pump Chip Set — SK70725/SK70721
17